lcd display driver circuit quotation

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Since the reference voltages are connected to all channels, many DACs may use the same reference voltage. The more DACs there are connected to a single reference voltage, the larger the required C-DAC settling time. This study simulates the settling time for different numbers of connected DACs using a 0.35-μm 5-V CMOS model. Figure 11 shows the simulated results where the settling time is measured at 99.9% of its final voltage for a full swing (0.266 V ~ 4.75 V). The settling time is 5.2 μs when 200 DACs are connected to a single reference voltage. Although a column driver IC contains several hundreds or even up to a thousand DACs, these DACs are distributed to 256 (28) reference voltages. This means that not all the DACs are connected to a single reference voltage. A typical UXGA (1600×1200) display has a pixel clock frequency of 162 MHz and a horizontal scanning time of 9.877 μs [4]. Hence, the proposed column driver is suitable for UXGA displays.

Due to the limited silicon area, the proposed LCD column driver has only four channels. The 10-bit LCD column driver with R-DAC and C-DAC was fabricated using a 0.35-μm 5-V CMOS technology. Table I shows the device sizes used in the proposed column driver, where Rtop, Rmid, Rbot, and Ri are designated in Figure 7. Figure 12 is a photograph of the die. Except for the resistor string of the R-DAC, the die area is 0.2×1.26 mm2 for four channels. Each RGB digital input code is 10-bits wide.

The Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) are typically measured for a DAC. However, it is difficult to determine these two specifications for a nonlinear DAC. To demonstrate the performance of the proposed circuit, the nonlinear gamma voltages are not applied to the R-string and the resistor values of the resistor string are made equal. Since an LCD panel needs several column drivers, the uniformity of different drivers is very important. Figure 13 shows the measured transfer curves of a DAC for eight off-chip column drivers. To show the deviation between different chips, Figure 14 provides an

enlarged view of the transfer curves, where the maximum deviation is 3.5 mV from the mean. This deviation is mainly due to process variations. The approach in this study uses no error correction. Hence, the deviation can be reduced by applying an offset canceling technique to the buffer amplifier. Figures 15(a) and (b) show the DNL values for positive and negative polarities, respectively. Figures 16(a) and (b) show the INL values for positive and negative polarities, respectively. The combination of R-DACs and C-DACs creates two groups of DNL values. The maximum DNL and INL values are 3.83 and 3.84 LSB, respectively. This study uses a 1-LSB voltage of 2.44mV to calculate the INL and DNL values. The linearity, however, is less important than the deviations between off-chip drivers for LCD drivers [2].

Figure 17 shows the measured output waveforms of two neighboring channels under dot inversion for the RGB digital inputs of ‘1111111111.’ Here, the voltage levels for negative and positive polarities are 0.266 V and 4.75 V, respectively. A load resistor of 5 kΩ and a capacitor of 90 pF were used. Figure 18 shows a similar waveform for ‘0000000000’ inputs, where the corresponding voltage levels for negative and positive polarities are 2.425 V and 2.598 V, respectively. These two figures show that the settling time is within 3 μs, which is smaller than that of previously published work [2] and standard UXGA displays [5]. Table II summarizes the performance of the proposed column driver IC. The average area per channel is 0.063 mm2, which is smaller than the reported areas of fully R-DAC-based column drivers [5, 8]. These experimental results show that the proposed column driver is suitable for UXGA LCD-TV applications.

Our invention relates to drive circuits for LCD displays, and more particularly to a circuit for driving the signal lines of a multi-level gray-scale LCD display.

As an example of an LCD display, FIG. 8 shows a schematic of an active-matrix thin-film transistor (TFT) color LCD display. A TFT liquid-crystal panel 100 has multiple gate lines Y1, Y2, . . . and multiple signal lines X1, X2, . . . which cross to form a matrix, and at each intersection point there is a thin film transistor for controlling a colored pixel (pixel) at that point. Gate line drivers G1, G2, . . . Gn are connected in parallel for driving the gate lines, and signal line (source) drivers S1, S2, . . . Sm are connected in parallel for driving the signal lines. A controller 102 controls the operation of each part. An image signal processing circuit 104 executes the necessary signal processing for the signals for the image to be displayed. A gray-scale voltage generating circuit 106 generates multiple-gray-scale voltages for enabling a full-color (multiple-gray-scale display).

Image signal processing circuit 104 supplies digital image data DX representing the gray-scale display of each pixel to the m signal line drivers. For example, with 64 gray-scale values, image data DL of 6 bits is provided to them signal line drivers from image signal processing circuit 104 for each red, green and blue (R,G,B) pixel. Controller 102 supplies various control or timing signals in synch with a horizontal synchronizing pulse HS and a vertical synchronizing pulse VS to the n gate line drivers and m signal line drivers. Gray-scale voltage generating circuit 104 provides multiple-level gray scale voltages corresponding to the 64 gray scale values achievable with the panel 100"s V-T (voltage-transmissivity) characteristics.

As shown in FIG. 9, a light source for backlighting is provided beneath lower polarizer 118 and the backlit display can be viewed from above through upper polarizer 120. Suppose the polarization axes of polarizer layers 118 and 120 are parallel to each other (e.g., both pointed into the page in FIG. 9). Assume that unactivated liquid crystal (no electric field applied) rotates the polarization axis of the backlight entering through polarizer layer 118 by 90° so it points to the left in FIG. 9 but activated liquid crystal (voltage applied between electrodes Pi,j and 116) does not rotate the backlight. In such case, the backlight (colored by filter 115) will only shine through polarizer layer 120 at those pixels where a voltage is applied between electrodes Pi,j and 116. If instead polarizer layers 118 and 120 are orthogonal to each other, the backlight will only shine through at those pixels where no voltage is applied.

The circuit configuration within liquid-crystal panel 100 is shown in FIG. 10. The liquid crystal material 114 sandwiched between each pixel electrode Pi,j and facing common electrode 116 forms a signal storage capacitor Cs. During each frame, the gate lines Y1, Y2, . . . are usually selected and driven active one line at a time in scan line order by the gate line drivers.

For example, if gate line Yi for line i is driven active, all transistors TFTi,1, TFTi,2, . . . of line i connected to gate line Yi are turned ON. Simultaneously, signal line drivers S1, S2, . . . output the analog gray-scale voltages for all the pixels of the i line, and these gray-scale voltages activate corresponding pixel electrodes Pi1, Pi2, . . . via signal lines X1, X2, . . . and “ON” transistors TFTi,1, TFTi,2, . . . .

Thus, a corresponding gray-scale voltage can be applied to each pixel electrode in one frame period, but to prevent degradation of the liquid-crystal molecules the polarity of the voltage applied must be alternated. In a TFT-LCD, there are two ways to apply alternating voltage to the liquid crystal material: the so-called common-fixed drive method and the common-inverting drive method.

The common-inverting drive method has the advantage of enabling a low-voltage driver to be used since the voltage amplification of the pixel electrode can be halved compared to the common-fixed process. However, it has the disadvantages that power consumption is high, because the large-capacitance common electrode 116 is driven with alternating current, and the display quality is inferior. In contrast, the common-fixed drive method has superior display quality and lower power consumption, although a low-voltage driver cannot be used. The common-fixed drive method is considered particularly suitable for large-screen TFT-LCD.

A conventional signal line driver circuit S using the common-fixed drive method is shown in FIG. 13. The circuit configuration of the drive portion for one signal line or one channel in such a signal line driver S is shown in FIG. 14.

In the conventional signal line driver S, an enable input signal EIO having pointing information, for example a “1”, is input from controller 102 into a shift register 140. This EIO signal is shifted within shift register 140 in accordance with a clock signal to sequentially designate the data storage positions for each channel portion of data register 142, enabling one line of image data DX from image data signal processing circuit 104 to be serially input into data register 142. Next, controller 102 provides a strobe signal ST to a data latch circuit 144 to input the one line of image data DX in parallel from data register 142 to the data latch circuit 144.

Then the image data DX in data latch 144 is input to a voltage level shifter circuit 145, which adjusts the signal voltage level, for example from 5 volts to 10 volts. The voltage-level adjusted one line of image data is then input from level shifter 145 to a digital-to-analog (D/A) converter supplied with all the gray-scale voltages by gray-scale voltage generating circuit 106.

In the common-fixed drive method, in order to apply each of the desired gray-level voltages for both positive and negative terminals with respect to the common fixed voltage, the number of gray-level voltages employed is twice the number of gray-scale values. Therefore, for 64 gray-scale values, gray-scale voltage generating circuit 106 must generate 128 reference voltages: 64 positive gray-scale voltages V1-V64 as well as 64 negative gray-scale voltages V64′-V1′.

As shown in FIG. 14, in each channel a D/A converter 146 jdecodes the 6-bit (for 64 levels) image data for one pixel and then selects and outputs the corresponding positive or negative gray-scale voltage Vj corresponding to the indicated display gray scale level. Gray-scale voltage Vj output from D/A converter 146 jis output to corresponding signal line Xj by an output amplifier 148 j, which is normally composed of a voltage follower. Because the common-fixed drive method employes twice as many gray-scale voltages as gray-scale values, the circuit scale, particularly the D/A converter, is substantially enlarged. Because the D/A converter has a voltage range including both the positive and negative gray-scale voltages, it operates with twice the normal voltage system, making it impossible to keep the area of each transistor element from becoming large. Therefore, the circuit scale increases noticeably as a result of the number of transistor elements doubling. When the chip area of the signal line driver becomes large, in addition to the chip cost increasing, satisfying the required specifications for the package (principally a tape carrier package) becomes difficult.

Also, in the common-fixed drive method output amplifier 148 jof each channel alternately operates between negative and positive voltage ranges. Consequently, the arithmetic amplifier of the voltage follower in output amplifier 148 jmust satisfy the linearity and offset characteristics in the source state, in which electric current is discharged from the output terminal, and the sink state, in which electric current is drawn to the output terminal, for all positive and negative gray-scale voltages, and very high precision is needed. This causes a great burden on manufacture and circuit design.

Therefore, an object of the present invention is to provide a signal line drive circuit for LCD displays that can alternate the voltage applied to the liquid crystal but has reduced chip size and circuit scale.

To achieve the objective, the first signal line drive circuit for LCD displays of our invention composed such that liquid crystals arranged in a matrix between a number of pixel electrodes and an opposing electrode are filled, each of the pixel electrodes is electrically connected to the corresponding signal line through the corresponding thin-film transistor, the control terminal of the thin-film transistor is electrically connected to the corresponding gate line, an opposing electrode voltage is applied to the opposing electrode, and gray-scale voltage, with a voltage level corresponding to the necessary display gray scale, is applied through the signal line and the thin-film transistor to each pixel electrode every time the gate line is driven, is provided with a first and, second D/A conversion means commonly connected to neighboring first and second signal lines of the LCD display and composed to respectively generate analog positive gray-scale voltages and negative gray-scale voltages in accordance with the opposing electrode voltage according to the digital gray-scale data representing the necessary display gray scale for an optional pixel electrode, and a switching means which alternately repeats, at a prescribed cycle, a first operation, in which the first digital/analog (D/A) conversion means generates the positive gray-scale voltage corresponding to the gray-scale data of the first signal line at the same time the second digital/analog conversion means generates negative gray-scale voltage corresponding to the gray-scale data of the second signal line, and a second operation, in which the first digital/analog conversion means generates the positive gray-scale voltage corresponding to the gray-scale data of the second signal line at the same time the second digital/analog conversion means generates the negative gray-scale voltage corresponding to the gray-scale data of the first signal line.

The second signal line drive circuit of our invention was composed so that, in the first signal line drive circuit, the switching means alternately repeats the first and second operations in the line cycle at which the gate line is driven by a sequential operation, and makes the pixel electrode alternately repeat the first and second operations in the frame cycle at which the gray-scale voltage is applied.

The third signal line drive circuit of our invention was composed so that, in the first or second signal line drive circuit, the output terminal of the first digital/analog conversion means is connected to the first and second signal lines via the switching means and a first output amplifier, which has an impedance converting function, and the output terminal of the second digital/analog conversion means is connected to the first and second signal lines via the switching means and a second output amplifier, which has an impedance converting function.

The fourth signal line drive circuit for LCD displays of our invention composed such that the liquid crystals arranged in a matrix between a number of pixel electrodes and an opposing electrode are filled, each of the pixel electrodes is electrically connected to the corresponding signal line through the corresponding thin-film transistor, the control terminal of the thin-film transistor is electrically connected to each corresponding gate line, an opposing electrode voltage is applied to the opposing electrode, and a gray-scale voltage, with a voltage level corresponding to the necessary display gray scale, is applied through the signal line and the thin-film transistor to each pixel electrode every time the gate line is driven, is provided with a first gray-scale voltage generating means, which has a positive polarity with respect to the opposing electrode voltage and generates a number of positive gray-scale voltages with voltage levels corresponding to each of all set display gray scales; a second gray-scale voltage generating means, which has a negative polarity with respect to the opposing electrode voltage and generates a number of negative gray-scale voltages with voltage levels corresponding to each of all set display gray scales; a gray-scale voltage selecting means, which is connected to the respective output terminals of the first and second gray-scale voltage generating means and alternately repeats, at a prescribed cycle, a first selection operation, which selects and outputs a number of positive gray-scale voltages from the first gray-scale voltage generating means, and a second selection operation, which selects and outputs a number of negative gray-scale voltages from the second gray-scale voltage generating means; and a digital/analog conversion means, which is provided with respect to each of the signal lines, decodes the digital gray-scale data representing the necessary display gray scale for one input pixel, selects one of the gray-scale voltages corresponding to the gray-scale data from the number of positive gray-scale voltages or the number of negative gray-scale voltages provided by the gray-scale voltage selecting means, and outputs it through the signal line.

In the first to third signal line drive circuits of our invention, alternating-current driving between the neighboring channels is carried out by making the first digital/analog conversion means dedicated to positive gray-scale voltages and the second digital/analog conversion means dedicated to negative gray-scale voltages in the drive part of two neighboring signal lines or channels and by alternately executing the first and second operations at a prescribed cycle using a switching means.

In the fourth signal line drive circuit of our invention, the digital/analog conversion means for each channel does not require that both positive and negative gray-scale voltages generated by the gray-scale voltage generating means be received simultaneously, so the necessary decoding operation can be carried out by inputting a gray-scale voltage of only one polarity corresponding to that of the alternating-current drive from the gray-scale voltage selecting means.

FIG. 3 is a block diagram of the main part of the driver when the signal line driver in the embodiment is applied to a TFT-LCD with 64 gray-scale values.

FIG. 6 is a block diagram of the main part of the driver when the signal line driver according to the second embodiment is applied to a TFT-LCD with 64 gray-scale values.

In the FIGS., 10, 10L, 10R are registers; 12, 12L, 12R first data latch circuits; 14L, 14R first switching circuits; 16, 16L, 16R second data latch circuits; 18, 18L, 18R level shifters; 20, 20L, 20R D/A converters; 22, 22L, 22R output amplifiers; and 24L, 24R are second switching circuits.

Some embodiments of our invention will be explained below with reference to FIGS. 1-7. FIG. 1 shows a circuit configuration of the main part of a signal line driver according to one embodiment of our invention. More specifically, it shows the construction of the drive part for two neighboring channels. This signal line driver can be used, for example, in the full-color TFT-LCD of an active-matrix system shown in FIG. 8. It will be assumed that the drive part for the two neighboring channels shown in the fig. drives signal lines Xj and Xj+1 of neighboring row number j and row number j+1 of liquid-crystal panel 100 shown in FIG. 8.

In FIG. 1, the drive part for the two neighboring channels has a pair of registers 10L and 10R, a pair of first data latch circuits 12L and 12R, a pair of first switching circuits 14L and 14R, a pair of second data latch circuits 16L and 16R, a pair of level shifters 18L and 18R, a pair of D/A converters 20L and 20R, a pair of output amplifiers 22L and 22R, a pair of second switching circuits 24L and 24R, and a pair of output pads 26L and 26R.

Registers 10L and 10R on the left side and the right side, respectively, correspond to the image data holding part for one pixel allocated to each corresponding channel in data register 142 of FIG. 13. In a prescribed cycle, for example, a line cycle, image data DXj and DXj+1 for one pixel having a prescribed number of bits is respectively input to first data latch circuits 12L and 12R on the left side and right side from registers 10L and 10R.

The output terminal of the left-side first data latch circuit 12L is connected to one (left side) input terminal of the left-side first switching circuit 14L and is connected to the other (right side) input terminal of the right-side first switching circuit 14R for each bit. The output terminal of the right-side first data latch circuit 12R is connected to one (left side) input terminal of the right-side first switching circuit 14R and is connected to the other (right side) input terminal of the left-side first switching circuit 14L for each bit.

First switching circuits 14L and 14R on the left side and the right side are alternately switched between one (left side) input terminal and the other (right side) input terminal according to alternating-current signal ST from a controller (not shown in the fig.). The output terminals of the left-side and right-side first switching circuits 14L and 14R are connected to the respective input terminals of the left-side and right-side second data latch circuits 16L and 16R.

The left-side and right-side second data latch circuits 16L and 16R input image data for one pixel from either the left-side first data latch circuit 12L or the right-side first data latch circuit 12R via the left-side and right-side first switching circuits 14L and 14R at a timing in synch with alternating-current signal ST. The output terminals of the left-side and right-side second data latch circuits 16L and 16R are connected respectively to the input terminals of the left-side and right-side D/A converters 20L and 20R via the left-side and right-side level shifters 18L and 18R.

Level shifters 18L and 18R convert the logical voltage (e.g., 5 V) of the image data to a high voltage (10 V) so that the circuit elements within D/A converters 20L and 20R can handle both positive and negative gray-scale voltages according to the common-fixed drive method.

All K positive gray-scale voltages V1-VK are supplied to the left-side D/A converter 20L from gray-scale voltage generating circuit 28. On the other hand, all K negative gray-scale voltages V′K-V′1 are supplied to right-side D/A converter 20R from gray-scale voltage generating circuit 28.

Gray-scale voltage generating circuit 28 is composed of, for example, a resistance-type voltage dividing circuit and a correction reference voltage (V) is supplied to the connection point (node) at the suitable location so that each gray-scale voltage with a voltage level corresponding to each display gray scale can be obtained according to the V-T characteristics of liquid-crystal panel 100.

The left-side D/A converter 20L is composed to decode the image data for one pixel that is input from the left-side level shifter 18L and to select and output a positive gray-scale voltage Vx with a voltage level corresponding to the display gray scale represented by the corresponding image data. On the other hand, the right-side D/A converter 20R is composed to decode the image data for one pixel that is input from the right-side level shifter 18R and to select and output a negative gray-scale voltage V′x with a voltage level corresponding to the display gray scale represented by the corresponding image data. The output terminals of the left-side and right-side D/A converters 20L and 20R are respectively connected to the input terminals of the left-side and right-side output amplifiers 22L and 22R.

The left-side output amplifier 22L is composed of a voltage follower of an arithmetic amplifier with an impedance converting function and is composed to operate in the sink state within the range of positive voltages. The output terminal of the left-side output amplifier 22L is connected to one (left side) input terminal of the left-side second switching circuit 24L and is connected to the other (right side) input terminal of the right-side second switching circuit 24R.

The right-side output amplifier 22R is composed of a voltage follower of an arithmetic amplifier with an impedance converting function and is composed to operate in the source state within the range of negative voltages. The output terminal of the right-side output amplifier 22R is connected to one (left side) input terminal of the right-side second switching circuit 24R and is connected to the other (right side) input terminal of the left-side second switching circuit 24L.

The left-side and right-side output terminals of second switching circuits 24L and 24R are respectively connected to signal lines Xj and Xj+1 (not shown in the fig.) of each corresponding channel via the left-side and right-side output pads 26L and 26R.

Next, the operation of the signal line driver according to this embodiment will be explained. In the TFT-LCD which includes this signal line driver, gate lines Y1, Y2, . . . of liquid-crystal panel 100 are normally selected one line at a time by a sequential operation within one frame period and driven in the active state by gate line drivers G1, G2, . . . Every time each gate line Yj is driven, gray-scale voltage Vj to be applied to each of the corresponding pixel electrodes on the pertinent line is output from output pad 26 of each channel in each signal line, driver.

Presently, it will be assumed that first switching circuits 14L and 14R and second switching circuits 24L and 24R are respectively switched to one (left side) input terminal when gate line Yi of line i is driven. At this time, image data DXi,j and DXi,j+1 representing the display gray scale of two pixels respectively positioned at line i, row j and line i, row (j+1) within liquid-crystal panel 100 are stored in first data latch circuits 12L and 12R.

In this case, at the same time the image data DXi,j for one pixel is being transmitted to the left-side second data latch circuit 16L via the left-side first switching circuit 14L from the left-side first data latch circuit 12L according to the timing of alternating-circuit signal ST, image data DXi,j+1 for one pixel is transferred to the right-side second data latch circuit 16R via the right-side first switching circuit 16R from the right-side first data latch circuit 12R.

Image data DXi,j and DXi,j+1 for one pixel input to the left-side and right-side second data latch circuits 16L and 16R is input respectively to the left-side and right-side D/A converters 20L and 20R via the left-side and right-side level shifters 18L and 18R.

Accordingly, positive gray-scale voltage Vj with a voltage level corresponding to the display gray scale represented by image data DXj is output from the left-side D/A converter 20L. On the other hand, negative gray-scale voltage V′j+1 with a voltage level corresponding to the display gray scale represented by image data DXi,j+1is output from the right-side D/A converter 20R.

The positive gray-scale voltage Vj output from the left-side D/A converter 20L is output to signal line Xj from the left-side output pad 26L via the left-side output amplifier 22L and second switching circuit 24L and is applied to pixel electrode Pi,j via TFTi,j of line i connected to the signal line Xj.

On the other hand, the negative gray-scale voltage Vj+1 output from the right-side D/A converter 20R is output to signal line Xj+1 from the right-side output pad 26R via the right-side output amplifier 22R and second switching circuit 24R and then applied to pixel electrode Pi,j+1 via TFTi,j+1 of line i connected to the signal line Xj+1.

Next, when gate line Yi+1 of line i+1 is driven, first switching circuits 14L and 14R and second switching circuits 24L and 24R are respectively switched simultaneously with the other (right side) input terminal according to the alternating-current signal ST.

In this way, simultaneously with the transfer of the image data DXi+1,j for one pixel corresponding to signal line Xi to the right-side second data latch circuit 16R via the right-side first switching circuit 14R from the left-side first data latch circuit 12L, image data DXi+1,j+1 for one pixel corresponding to signal line Xi+1 is transferred to the left-side second data latch circuit 16L via left-side first switching circuit 14L from the right-side first data latch circuit 12R.

Image data DXi+1,j+1 for one pixel input to the left-side and right-side second data latch circuits 16L and 16R is respectively input to the left-side and right-side D/A converters 20L and 20R via the left-side and right-side level shifters 18L and 18R.

In this way, positive gray-scale voltage Vj+1 with a voltage level corresponding to the display gray scale represented by image data DXi+1,j+1 is output from the left-side D/A converter 20L. On the other hand, the negative gray-scale voltage V′j with a voltage level corresponding to the display gray scale represented by image data DXi+1,J is output from the right-side D/A converter 20R.

The positive gray-scale voltage Vj+1 output from the left-side D/A converter 20L is output to signal line Xj+1 from the right-side output pad 26R via the left-side output amplifier 22L and the right-side second switching circuit 24R, and applied to corresponding pixel electrode Pi+1,j+1 via TFTi+1,j+1 of line i+1 connected to the signal line Xj+1.

On the other hand, the negative gray-scale voltage V′j output from the right-side D/A converter 20R is output to signal line Xj from the left-side output pad 26L via the right-side output amplifier 22R and the left-side second switching circuit 24L, and is applied to the corresponding pixel electrode Pi+1,j via TFTi+1,j of line i+1 connected to the signal line Xj.

Thereafter, the operation is repeated for two lines. In this way, the polarity of the gray-scale voltage reverses for each pixel in the Y direction of liquid-crystal panel 100. Also, the polarity of the gray-scale voltage reverses (between two neighboring signal lines Xj and Xj+1 for each pixel in the X direction. By thus reversing the polarity of the gray-scale voltage in the neighboring signal lines and pixel electrodes, the currents flowing through the pixel electrode, opposing electrode, etc., are offset, and decreases in the display quality is thereby suppressed.

Switching circuits 14L, 14R, 24L, and 24R are controlled so as to be switched for each frame (namely, so that the position of switching circuits 14L, 14R, 24L, and 24R reverses for each frame when gate line Yi of each line is driven) according to alternating-current signal ST. With this type of reversal of the frame cycle, an electrode voltage waveform according to the common-fixed drive method like that shown in FIG. 11 is obtained.

As noted above, in the signal line driver according to the present embodiment, the common-fixed drive method) and dot reversal (reversal of every pixel) is realized by making the left-side D/A converter 20L and output amplifier 22L dedicated to positive gray-scale voltages and making the right-side D/A converter 20R and output amplifier 22R dedicated to negative gray-scale voltages in the drive part for two neighboring channels, and switching first switching circuits 14L and 14R provided prior to D/A converters 20L and 20R and second switching circuits 24L and 24R provided after output amplifiers 22L and 22R in a prescribed cycle, for example, line cycle and frame cycle. D/A converters 20L and 20R for one channel only have to handle a number of gray-scale voltages of one polarity equal to the number of display gray scales so only half of the transistor elements are necessary compared to the conventional technology and the circuit scale can be decreased by half.

Output amplifiers 22L and 22R must operate normally in either the sink state or the source state for the range of gray-scale voltages for one polarity. Consequently, along with the circuit scale for one channel becoming small in output amplifiers 22L and 22R, the dynamic range, linearity, and offset characteristics can be easily obtained, and the burden on the manufacture process and circuit design can be reduced.

In the aforementioned embodiment, output switching of switching circuits 24L and 24R is mutually executed between two neighboring channels, but the same effect can be obtained even with a simultaneous switching system like that shown in FIG. 2. In FIG. 2, the construction of each part other than the switching circuit is the same as the construction of each corresponding part in FIG. 1.

The circuit configuration of the main part of the driver in a case in which the signal line driver of the present embodiment is applied to a TFT-LCD of 64 gray-scale values, more specifically, the circuit configuration of a D/A converter is shown in FIG. 3. Parts that are the same as those in FIG. 1 are indicated with the same reference numerals.

In this constructional example, two sets of image data DXj and DXj+1, which represent the display gray scale for one pixel with 6 bits, are selectively input to the left-side and right-side D/A converters 20L and 20R via registers 10L and 10R to level shifters 18L and 18R.

Initial step switch array 1 is supplied with all 64 positive gray-scale voltages V1-V64 from gray-scale voltage generating circuit 28. Out image data DXj or DXj+1 of 6 bits provided from the left-side level shifter 18L, the upper-order 3 bits are input to upper-order decoder 20 LA. Upper-order decoder 20 LAselects one set 8 from the 64 positive gray-scale voltages V1-V64 input to initial-step switch array 1 and transmits it to final step switch array 2. The lower-order 3 bits of image data DXj or Dxj+1 from the left-side level shifter 18L are input to lower-order decoder 20 LB. Lower order decoder 20 LBselects one Vj or Vj+1 from the 8 gray-scale voltages input to switch array 2 and outputs it from switch array 2.

The right-side D/A converter 20R has the same circuit configuration as the left-side D/A converter 20L and each part operates in the same manner as each corresponding part of the left-side D/A converter 20L. However, all 64 negative gray-scale voltages V′64-V′1 are supplied to, initial step switch array 1′ from gray-scale voltage generating circuit 28. Therefore, when image data DXj+1 or DXj of 6 bits is input to decoder 20 RAand 20 RBfrom the right-side level shifter 18R, negative gray-scale voltage V′j+1 or V′j with a voltage level corresponding to the display gray scale expressing represented by the corresponding image data is output from final step switch array 2.

One example of a circuit layout for the drive part for two channels in FIG. 2 in a semiconductor integrated circuit is shown in FIG. 4B. FIG. 4A is a circuit layout for the drive part for two channels in a conventional signal line driver.

Both are for 64 gray scales, but in the conventional driver A, the D/A converter for one channel handles 128 positive and negative gray-scale voltages, whereas, in the circuit of the present embodiment B, the D/A converter for one channel only has to handle 64 positive or negative gray-scale voltages, reducing the circuit area by half. Also, even in the output amplifier for one channel, which has a circuit configuration for both sink and source use in the conventional driver A, circuit configuration for either sink or source use can be used in the circuit of the present embodiment B, making the circuit area is much smaller.

In the aforementioned embodiment, various modifications are possible. For example, D/A converter 20 can be constituted with an optional logic circuit and can be composed with a ROM decoder. Various formats can also be applied for the data transfer means of register 10, data latch circuits 12 and 16, etc. Level shifter 18 can be omitted depending on necessity when, for example, the signal line driver of the present embodiment utilizes the common-inverting drive method. Also, even output amplifier 22 can be omitted depending on necessity when, for example, impedance matching can be achieved between the liquid-crystal panel and the driver. Also, the switching cycle of switching circuits 14 and 24 can be optionally set and switched, for example, for every few lines.

Next, another embodiment of our invention will be explained with reference to FIGS. 5-7. FIG. 5 shows the construction of the drive part for one channel in the signal line driver according to this second embodiment. The main characteristic in the construction of this embodiment is that selecting circuit 30 is provided between gray-scale voltage generating circuit 28 and D/A converter 20.

This selecting circuit 30 has a number of K first input terminals a which input all positive gray-scale voltages V1-VK from the positive gray-scale voltage generation part of gray-scale voltage generating circuit 28 and a number of K second input terminals b which input all negative gray-scale voltages V′K-V′1 from the negative gray-scale voltage generation part of gray-scale voltage generating circuit 28, and alternately outputs positive gray-scale voltages V1-VK or negative gray-scale voltages V′1-V′K at a prescribed cycle to alternating-current signal ST.

According to the construction, D/A converter 20 does not have to input both positive polarity and negative gray-scale voltages simultaneously and only has to execute the necessary decoding operation by inputting gray-scale voltages of one polarity corresponding to each polarity of the alternating-current drive from selecting circuit 30, allowing the circuit scale to be small. Naturally, output amplifier 22′ operates with respect to both positive polarity and negative gray-scale voltages so a circuit configuration with both the sink and source functions like in the conventional technology is realized.

In the signal line driver according to this embodiment, the drive part for each channel is parallel and independent and switching circuits 14 and 24 are not provided as in the aforementioned embodiment.

The circuit configuration of the main part of the driver when the signal line driver of this embodiment is applied to, for example, a TFT-LCD with 64 gray-scale values, more specifically, the circuit configuration of a D/A converter, is shown in FIG. 6.

The signal line driver of this embodiment outputs gray-scale voltages of temporarily identical polarity from the driver part for all channels. To execute dot reversal using this type of signal line driver, arrange signal line drivers SU and SL respectively on both sides (upper side and lower side) of liquid-crystal panel 100 as shown in FIG. 7 and allocate two neighboring signal lines to the upper signal line driver SU and lower signal line driver SL.

In FIG. 7, the aforementioned selecting circuit 30 is built into each signal driver SU and SL. To execute dot reversal, switching control must be executed such that selecting circuit 30 in each lower signal line driver SL1, SL2, . . . , selects negative gray-scale voltages V′K-V′1 when switching circuit 30 in each upper signal line driver SU1, SU2, . . . , is selecting positive gray-scale voltages V1-VK, and switching circuit 30 in each lower signal line driver SL1, SL2, . . . , selects positive gray-scale voltages V1-VK when switching circuit 30 in each upper signal line driver SU1, SU2, . . . , is selecting negative polarity gray scale voltages V′K-V′1.

In FIGS. 1, 4, and 5, 20L, 20R, 20, and 146 jrepresent D/A converters, but these are essentially decoder circuits and are considered D/A converters based on the fact that digital data is being converted into analog voltages.

As explained above, according to the signal line drive circuit for LCD displays of our invention, the circuit scale of the analog digital converting means for selectively outputting an analog gray-scale voltage complying with the digital image data in the drive part for each channel can be made quite small. Furthermore, the circuit scale of the output amplifier in the drive part for each channel can be made small and can easily satisfy the characteristics/specifications, such as the dynamic range, etc. Therefore, simplification in the manufacture and design and considerable reduction in the chip size can be realized.

Our 64128LX monochrome graphic LCD module has a viewing area of approximately 60 x 30 mm. This LCD is suitable for a wide variety of applications and is available with several different backlight colors. The COG IC is the Sitronix ST7565R. This LCD has a FPCinterface.

The ST7565R is a single-chip dot matrix LCD driver that can be connected directly to a microprocessor bus. 8-bit parallel or 4-line SPI display data sent from the microprocessor is stored in the internal display data RAM and the chip generates a LCD drive signal independent of the microprocessor. Because the chips in the ST7565R contain 65x132 bits of display data RAM and there is a 1-to-1 correspondence between the LCD panel pixels and the internal RAM bits, these chips enable displays with a high degree of freedom. The ST7565R chips contain 65 common output circuits and 132 segment output circuits, so that a single chip can drive a 65x132 dot display (capable of displaying 8 columns x 4 rows of a 16x16 dot kanji font).

The 128240D is our largest standard monochrome graphic LCD. The viewing area is 92 x 53 mm and offers grey-scale performance. This LCD module is most commonly paired with a white LED backlight.

The ST7529 is a driver & controller LSI for 32 gray scale graphic dot-matrix liquid crystal display systems. It generates 255 Segment and 160 Common driver circuits. This chip is connected directly to a microprocessor, accepts Serial Peripheral Interface (SPI), 8-bit/16-bit parallel or IIC display data and stores in an on-chip display data RAM. It performs display data RAM read/write operation with no external operating clock to minimize power consumption. In addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components.

12, the driver board can increase the remote control function (need to achieve through the software) the existing procedures only need to add remote control, direct use

13, the driver plate can automatically detect, and display the relevant input voltage information ---- note, this function for custom function, need to contact my company

19. Driver board VCOM voltage adopts potentiometer adjustment design, which can adapt to more LCD screens, and the adjustment is convenient and simple

In this tutorial, I’ll explain how to set up an LCD on an Arduino and show you all the different ways you can program it. I’ll show you how to print text, scroll text, make custom characters, blink text, and position text. They’re great for any project that outputs data, and they can make your project a lot more interesting and interactive.

The display I’m using is a 16×2 LCD display that I bought for about $5. You may be wondering why it’s called a 16×2 LCD. The part 16×2 means that the LCD has 2 lines, and can display 16 characters per line. Therefore, a 16×2 LCD screen can display up to 32 characters at once. It is possible to display more than 32 characters with scrolling though.

The code in this article is written for LCD’s that use the standard Hitachi HD44780 driver. If your LCD has 16 pins, then it probably has the Hitachi HD44780 driver. These displays can be wired in either 4 bit mode or 8 bit mode. Wiring the LCD in 4 bit mode is usually preferred since it uses four less wires than 8 bit mode. In practice, there isn’t a noticeable difference in performance between the two modes. In this tutorial, I’ll connect the LCD in 4 bit mode.

Here’s a diagram of the pins on the LCD I’m using. The connections from each pin to the Arduino will be the same, but your pins might be arranged differently on the LCD. Be sure to check the datasheet or look for labels on your particular LCD:

Also, you might need to solder a 16 pin header to your LCD before connecting it to a breadboard. Follow the diagram below to wire the LCD to your Arduino:

There are 19 different functions in the LiquidCrystal library available for us to use. These functions do things like change the position of the text, move text across the screen, or make the display turn on or off. What follows is a short description of each function, and how to use it in a program.

TheLiquidCrystal() function sets the pins the Arduino uses to connect to the LCD. You can use any of the Arduino’s digital pins to control the LCD. Just put the Arduino pin numbers inside the parentheses in this order:

This function sets the dimensions of the LCD. It needs to be placed before any other LiquidCrystal function in the void setup() section of the program. The number of rows and columns are specified as lcd.begin(columns, rows). For a 16×2 LCD, you would use lcd.begin(16, 2), and for a 20×4 LCD you would use lcd.begin(20, 4).

This function clears any text or data already displayed on the LCD. If you use lcd.clear() with lcd.print() and the delay() function in the void loop() section, you can make a simple blinking text program:

Similar, but more useful than lcd.home() is lcd.setCursor(). This function places the cursor (and any printed text) at any position on the screen. It can be used in the void setup() or void loop() section of your program.

The cursor position is defined with lcd.setCursor(column, row). The column and row coordinates start from zero (0-15 and 0-1 respectively). For example, using lcd.setCursor(2, 1) in the void setup() section of the “hello, world!” program above prints “hello, world!” to the lower line and shifts it to the right two spaces:

You can use this function to write different types of data to the LCD, for example the reading from a temperature sensor, or the coordinates from a GPS module. You can also use it to print custom characters that you create yourself (more on this below). Use lcd.write() in the void setup() or void loop() section of your program.

The function lcd.noCursor() turns the cursor off. lcd.cursor() and lcd.noCursor() can be used together in the void loop() section to make a blinking cursor similar to what you see in many text input fields:

Cursors can be placed anywhere on the screen with the lcd.setCursor() function. This code places a blinking cursor directly below the exclamation point in “hello, world!”:

This function creates a block style cursor that blinks on and off at approximately 500 milliseconds per cycle. Use it in the void loop() section. The function lcd.noBlink() disables the blinking block cursor.

This function turns on any text or cursors that have been printed to the LCD screen. The function lcd.noDisplay() turns off any text or cursors printed to the LCD, without clearing it from the LCD’s memory.

This function takes anything printed to the LCD and moves it to the left. It should be used in the void loop() section with a delay command following it. The function will move the text 40 spaces to the left before it loops back to the first character. This code moves the “hello, world!” text to the left, at a rate of one second per character:

Like the lcd.scrollDisplay() functions, the text can be up to 40 characters in length before repeating. At first glance, this function seems less useful than the lcd.scrollDisplay() functions, but it can be very useful for creating animations with custom characters.

lcd.noAutoscroll() turns the lcd.autoscroll() function off. Use this function before or after lcd.autoscroll() in the void loop() section to create sequences of scrolling text or animations.

This function sets the direction that text is printed to the screen. The default mode is from left to right using the command lcd.leftToRight(), but you may find some cases where it’s useful to output text in the reverse direction:

This code prints the “hello, world!” text as “!dlrow ,olleh”. Unless you specify the placement of the cursor with lcd.setCursor(), the text will print from the (0, 1) position and only the first character of the string will be visible.

This command allows you to create your own custom characters. Each character of a 16×2 LCD has a 5 pixel width and an 8 pixel height. Up to 8 different custom characters can be defined in a single program. To design your own characters, you’ll need to make a binary matrix of your custom character from an LCD character generator or map it yourself. This code creates a degree symbol (°):