tft lcd driving circuit in stock

INT028ATFT and INT028ATFT-TS are embedded display driver boards based on our 2.8 inch 240 x 320 RGB resolution TFT display module. Mounted on the embedded board is the RAIO RA8872 LCD controller that offers the following features and benefits:

INT018ATFT is an embedded display driver board based on our 1.8 inch 128 x 160 RGB resolution TFT display module. Mounted on the embedded board is the RAIO RA8872 LCD controller that offers the following features and benefits:

A wide variety of lcd driver circuit options are available to you, such as 1 oz, 2 oz and 3 oz.You can also choose from consumer electronics pcba, home appliance pcba and smart electronics pcba lcd driver circuit,

Tianma Display model TM078L1280 is a color active matrix thin film transistor (TFT) liquid crystal display (LCD) that uses amorphous silicon TFT as a switching device. This model is composed of a TFT LCD panel, a driving circuit and a back light system. This TFT LCD has a 7.84 inch diagonally measured active display area with (400 horizontal by 1280 vertical pixel) resolution.

Panox Display values every opportunity to cooperate with clients, because TFT-LCD is very fragile, so we provide a solid package and the fastest way to ship. Panox Display has seven years experience of in international trade and served more than 1000 clients all over World.

To make your development of the TFT-LCD driver more smooth, Panox Display will provide free connectors and an adapter board, engineers can directly fly lines to the main board.

But Panox Display is not a school, if customers don`t know the basic knowledge to design circuit board, we suggest using our controller board to drive the display.

Due to the limited silicon area, the proposed LCD column driver has only four channels. The 10-bit LCD column driver with R-DAC and C-DAC was fabricated using a 0.35-μm 5-V CMOS technology. Table I shows the device sizes used in the proposed column driver, where Rtop, Rmid, Rbot, and Ri are designated in Figure 7. Figure 12 is a photograph of the die. Except for the resistor string of the R-DAC, the die area is 0.2×1.26 mm2 for four channels. Each RGB digital input code is 10-bits wide.

The Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) are typically measured for a DAC. However, it is difficult to determine these two specifications for a nonlinear DAC. To demonstrate the performance of the proposed circuit, the nonlinear gamma voltages are not applied to the R-string and the resistor values of the resistor string are made equal. Since an LCD panel needs several column drivers, the uniformity of different drivers is very important. Figure 13 shows the measured transfer curves of a DAC for eight off-chip column drivers. To show the deviation between different chips, Figure 14 provides an

enlarged view of the transfer curves, where the maximum deviation is 3.5 mV from the mean. This deviation is mainly due to process variations. The approach in this study uses no error correction. Hence, the deviation can be reduced by applying an offset canceling technique to the buffer amplifier. Figures 15(a) and (b) show the DNL values for positive and negative polarities, respectively. Figures 16(a) and (b) show the INL values for positive and negative polarities, respectively. The combination of R-DACs and C-DACs creates two groups of DNL values. The maximum DNL and INL values are 3.83 and 3.84 LSB, respectively. This study uses a 1-LSB voltage of 2.44mV to calculate the INL and DNL values. The linearity, however, is less important than the deviations between off-chip drivers for LCD drivers [2].

Figure 17 shows the measured output waveforms of two neighboring channels under dot inversion for the RGB digital inputs of ‘1111111111.’ Here, the voltage levels for negative and positive polarities are 0.266 V and 4.75 V, respectively. A load resistor of 5 kΩ and a capacitor of 90 pF were used. Figure 18 shows a similar waveform for ‘0000000000’ inputs, where the corresponding voltage levels for negative and positive polarities are 2.425 V and 2.598 V, respectively. These two figures show that the settling time is within 3 μs, which is smaller than that of previously published work [2] and standard UXGA displays [5]. Table II summarizes the performance of the proposed column driver IC. The average area per channel is 0.063 mm2, which is smaller than the reported areas of fully R-DAC-based column drivers [5, 8]. These experimental results show that the proposed column driver is suitable for UXGA LCD-TV applications.

The present invention relates to Liquid Crystal Displays (LCDs), more specifically, to a Thin Film Transistor-Liquid Crystal Display (TFT-LCD) driver circuit and LCD devices. BACKGROUND

Current TFT-LCD technologies have been trending toward higher levels of integration, higher resolution and multi-grayscale capabilities. As such, the TFT-LCD driver circuit device area and power consumption have increased accordingly, leading to higher manufacturing costs. In a traditional TFT-LCD driver circuit, a source drive buffer or latch of the source drive chip occupies a large footprint and consumes a considerable amount of power.

An object according to an embodiment of the present invention is to eliminate the large area occupation and the high power consumption of the source drive buffer in the traditional TFT-LCD driver circuit. Accordingly, a first embodiment discloses a TFT-LCD driver circuit including: a gate driver adapted to control turning on of a Thin Film Transistor (TFT); a grayscale voltage generation circuit capable of providing a grayscale voltage for display points; a timing circuit configured to provide timing signals; a bias circuit configured to provide bias voltage signals; and a source driver operable to charge the display points according to the grayscale voltage. The source driver includes: a source drive latch configured to store data for the display points; a source drive buffer; and a Digital to Analog Converter (DAC) configured to output the grayscale voltage to the source drive buffer according to the stored display data. The source drive buffer includes an Operational Amplifier (OPA), which includes first and second differential amplifiers, The differential amplifiers operate alternatively according to the timing signals and bias voltage signals, and buffer and output voltage signals outputted from the DAC by means of a voltage follower mechanism for charging the display points.

The first differential amplifier includes: a first differential circuit having two N-channel Metal Oxide Semiconductor (NMOS), wherein the gate of the first NMOS is coupled to the output of the DAC and the gate of the second NMOS is coupled to the output of the OPA; a first current mirror source being a loader of the first differential circuit; an end of current source; an output stage which includes a NMOS and a PMOS, the gate of the NMOS and the end of current source being controlled by the bias voltage signals, the gate of the PMOS being coupled to the output of the first current mirror source; and a power down PMOS operable to turning on and off the OPA by timing signals.

The second differential amplifier includes: a second differential circuit having two P-channel Metal Oxide Semiconductor (PMOS), wherein the gate of the first PMOS is coupled to the output of the DAC while the gate of the second PMOS is coupled to the output of the OPA; a second current mirror source being a loader of the second differential circuit; an end of current source; an output stage which includes a PMOS and a NMOS, the gate of the PMOS and the end of current source being controlled by the bias voltage signals, the gate of the NMOS being coupled to the output of the second current mirror source; and a power down NMOS which is applied for turning on and off OPA by timing signals.

Fig. 6 illustrates a diagram of a control circuit for bias voltages PBIASL and NBIASL of the TFT-LCD driver circuit according to an embodiment of the present invention;

Fig. 7 illustrates waveforms of the bias voltages PBIASL and NBIASL of the TFT-LCD driver circuit according to an embodiment of the present invention;

The source drive buffer of the TFT-LCD driver circuit of the presently disclosed embodiments can be formed with two basic differential amplifiers and a CMOS transmission gate. The two differential amplifiers can be turned on alternatively according to timing of control signals, adjust an output voltage through the COMS transmission gate, and charge pixels in a row to the required voltage level until scanning of the pixels in the row is completed.

Fig. 1 illustrates a typical circuit diagram of a TFT panel. The TFT panel provides a plurality of display points forming an n×m matrix with n rows (G1, G2, G3, ..., Gn) and m columns (S1, S2, S3, ...,Sm), wherein each display point represents a Twisted Nematic Liquid Crystal Display (TN-LCD) point and includes a TFT, a parallel plate capacitor (not shown) formed with upper and lower conductive glasses and a storage capacitor, the parallel plate capacitor and storage capacitor having parallel coupling. If a color filter has three basic colors, a basic pixel display unit needs to be provided with three such display points corresponding to red, green and blue, i.e. the three basic primary colors. At a specific time, the gate driver outputs a drive pulse to turn on all TFT"s in a row. At the same time, the source driver charges the display points in the row to the necessary voltage. When the charging of the row is completed, the gate driver turns off the TFT"s in the row, turns on TFT"s in the next row, and charges the display points in the next row.

Fig. 2 illustrates a circuit diagram of a TFT-LCD driver circuit according to the first embodiment of the present invention. For the sake of description, only TFT-components of the LCD driver circuit involved in the invention are shown in Figure 2. The TFT-LCD driver circuit includes gate and source drivers, a grayscale voltage generator with a timing generator (not shown), and a bias voltage generator (not shown).

As shown in Fig. 2, TFTs N1-Nm are provided in the row. A gate of each of the TFTs is turned on or off under the control of the dirve pulse outputted from the gate driver, m sources of the TFTs are respectively coupled to outputs of source drivers, and m drains of the TFTs are respectively coupled to storage capacitors Cs1-Csm. When the row is canned, all the TFTs of the row are turned on by the drive pulse outputted from the gate driver. At the same time, latch data stored within the source drive latch is decoded and converted by Digital to Analog Converters (DACs), to select a grayscale voltage generator to generate the grayscale voltage to be supplied to each display point. The grayscale voltage is transmitted through the source drive buffer and a corresponding one of the transmission gates T1-Tm to charge a display electrode of the respective display point, thereby driving the LCD panel. As shown in Fig. 2, m source drive buffers (within the dashed outline) corresponds to m display points in the row under scan, and each source drive buffer includes an operational amplifier (OPA).

Fig. 3 illustrates the relationship between input and output signals of the OPA of the source drive buffer as shown in Fig. 2. Specifically, the OPA receives the voltage signal PIN from the corresponding DAC, latches the voltage signal PIN and charges the corresponding display electrode through the corresponding one of the transmission gates T1-Tm (as shown in Fig. 2) under the control of timing signals PDP, PDP_N, PDN, PDN_N and bias voltage signals PBIASL and NBIASL. The output OUT of the OPA is short connected to a feedback NIN, causing the output voltage to be fed back to the feedback NIN of the OPA, and the entire OPA is equivalent to a voltage follower. The various timing signals are generated by the timing generators of the TFT-LCD driver circuit.

Fig. 4 is a circuit diagram of the OPA according to an embodiment of the present invention. The OPA includes a first differential amplifier (OPAN) and a second differential amplifier (OPAP), which operate alternatively under the control of timing signals. The input stage of the OPAN includes a first differential circuit 41 having two N-channel Metal Oxide Semiconductors (NMOSs), and the gates of the NMOSs are coupled to the voltage output PIN of the DAC and the output OUT of the source drive buffer. The sources of the two NMOSs can be coupled to each other to form a coupled source pair, and connected with the ground potential VSS of the driver circuit via a first switch Q1. Depending on the bias at the first switch Q1, the drains of the first differential circuit 41 are coupled to the power terminal VDD of the drive circuit via a first current mirror source 42. With the first current mirror source 42 as the load, the output impedance is improved to obtain a higher gain. The output stage of the OPAN is of a simple co-source structure to improve the range of the output waveforms, and is formed with a second switch Q2 and a third switch Q3 coupled in series, and the coupling node between the switches Q2 and Q3 is the output OUT of the OPA. The gates of the second switch Q2 and the first switch Q1 are coupled in series, and turned on under the control of the bias voltage signal NBIASL. The gate of the third switch Q3 is coupled to the source of the first current mirror source 42, and also to the power terminal VDD of the drive circuit via a fourth switch Q4. The gate of the fourth switch Q4 can be turned on under the control of the timing signal PDN_N, to control and ensure that the OPAN is working properly.

Similarly, the input stage of the OPAP includes a second differential circuit 43 formed with two P-channel Metal Oxide Semiconductors (PMOSs), and the gates of the two PMOSs are coupled to the voltage output PIN of the DAC and the output OUT of the source drive buffer. The sources of the two PMOSs are connected with the power terminal VDD of the drive circuit via a fifth switch Q5. Depending on the bias at the fifth switch Q5, the drains of the second differential circuit 43 are coupled to the ground potential VSS of the driver circuit via a second current mirror source 44. With the second current mirror source 44 as the load, the output impedance is improved to obtain a higher gain. The output stage of the OPAP is of a simple co-source structure, and includes sixth and seventh switches Q6, Q7 coupled in series, and the coupling node between the switches Q6 and Q7 is the output OUT of the OPA. The gates of the sixth switch Q6 and the fifth switch Q5 are coupled in series, and are turned on under the control of the bias voltage control signal PBIASL. The gate of the seventh switch Q7 is coupled to the source of the second current mirror source 44, and also to the ground potential VSS of the driver circuit via an eighth switch Q8. The gate of the eighth switch Q8 can be turned on under the control of the timing signal PDP, to control the operation status of the OPAP.

Figs. 6 and 7 respectively illustrate a control circuit diagram and waveforms of the bias voltages PBIASL and NBIASL in the TFT-LCD driver circuit according to an embodiment of the present invention. The generator which generates the bias voltage signals PBIASL and NBIASL serves as a global circuit module which provides the bias voltages for all source drive buffers in the TFT-LCD driver circuit, while the other circuit modules in the TFT-LCD driver circuit are provided with bias voltages by the bias voltage signals PBIAS and NBIAS.

With reference to Figs. 2-8, the working principles of the source drive buffer according to an embodiment of the present invention during the time for scanning a row, i.e. periods tl+t2+t3, are described as follows. The data as stored in the source drive latch are decoded and converted by the DAC, to select the grayscale voltage generator to generate the appropriate grayscale voltage. During period t1, the first switch Q1 and the second switch Q2 are turned on by the bias voltage signal NBIASL, and both the first differential circuit 41 and the first current mirror source 42 start to operate. Because the PDN_N is at a high voltage level, the fourth switch Q4 is off, the OPAN is able to function normally, and the voltage generated by the grayscale voltage generator is buffered and outputted. Further, because the bias voltage signal PBIASL is at a high voltage level, the fifth switch Q5 is off, and because the PDP is at a high voltage level, the eighth switch Q8 is on, thereby pulling down or lowering the gate voltage of the seventh switch Q7 to the low voltage level VSS, turning off the OPAP. That is, the OPAN is in operation during the period t1. During the period t2, the OPAP is operative, the control principle of which is opposite to that during the period t1, and thus will not be elaborated further herein. Because the entire OPA is equivalent to a voltage follower, during the periods t1 and t2, the voltage following approach ensures that the level of the output OUT is equal to the level of the input PIN. It should be appreciated by one skilled in the art that the previously described scenario may be reversed by means of timing control such that the OPAP is in operation during period t1 while the OPAN is in operation during period t2. The operational functions of the amplifiers and corresponding grayscale voltages are similar to those described above and thus will not be elaborated further herein.

In the embodiments described above, the first differential amplifier OPAN is effective when the voltage rises, i.e. dominant when the input voltage changes from a low level to a high level, while the second differential amplifier OPAP is effective when the voltage decreases, i.e. dominant when the input voltage changes from a high level to a low level. Therefore, only one differential amplifier is contributing to the system during the time for scanning one row, thereby causing differentiation between the output waveform and the actual input waveform of the buffer. However, after adjustments by the grayscale voltage, the differentiation will not influence the display on the LCD, because the voltage in the storage capacitor Cs of the LCD panel just before the TFT is turned off is stored, that is, the output of the cache has reached or been close to an ideal value when N1 is changed from the higher voltage to the lower voltage.

Additionally, to expand the range of the common-mode input, mixed use of an NMOS differential pair (first differential amplifier) and a PMOS differential pair (second differential amplifier) may be incorporated as a two-tier operational amplifier. The two operational amplifiers operate in a time division mode through timing control, thereby effectively improving the range of the input voltage. Further, because of the reduced complexity of the source drive buffer, circuitry dimensions can be reduced and less area or die size would be required. Furthermore, power consumption can also be reduced because the two differential operational amplifiers operate in a time division mode.