pixelworks lcd panel controller free sample

Pixelworks (Tualatin, OR) has scored a supply contract from IBM (White Plains, NY), which has selected the company"s ImageProcessor solution to power its high-resolution TFT-LCD panel. Commercially available ImageProcessors are capable of running the QXGA-resolution display at 2,048 x 1,536 pixels using 24-bit color and at 60 MHz refresh rate, which requires more than 5 Gb/s of bandwidth. The single-chip display controller architecture provides capabilities such as image resizing, automatic image optimization, and high-performance video, including HDTV.

IBM"s 20.8-in ITQX20 TFT-LCD panel is the world"s first commercially available QXGA-resolution display. With a density of 123 pixels/in, the panel displays the equivalent content of four XGA-resolution monitors on a single screen.

The Pixelworks display controller platform can be used with advanced display product including monitors, projectors and televisions using LCD, gas plasma, and Digital Light Processing (DLP) technologies.

FIG. 2 is a block diagram of a display system 100. Referring to FIG. 2, the system 100 includes an analog signal receiver 120 for receiving an analog image data signal 110, e.g., composite video RGB, Y, PB, and PYor S-video signals, from a source 102. The source 102 may be a personal computer 107, a digital video disk player 105, set top box (STB) 103, or any other device capable of generating the analog image data signal 110. Likewise, the receiver 120 decodes an analog video signal 112, e.g., composite video RGB, Y, PB, and PYor S-video signals, from a video source 104. The video source 104 may be a video camcorder, tape player, digital video disk (DVD) player, or any other device capable of generating the analog video signal 112. The video source 104 may read (or play) external media 101. In an embodiment, a DVD player 104 plays the DVD 101. In another embodiment, a VHS tape player 104 plays a VHS tape 101. The decoder 120 converts the analog image signal 110 or analog video signal 112 into the digital video signal 109 and provides it to the panel controller 150. The decoder 120 is any device capable of generating digital video signal 109, e.g., in Y/C or CVBS format, from the analog image data 110 or analog video signal 112.

The digital signal receiver 124 may include a modem or network interface card (NIC), a Digital Visual Interface (DVI) or high definition multimedia interface (HDMI), a digital modem or any device capable of receiving data 114 from a network 106, any device capable of receiving a signal 118 transmitted wirelessly by any other device, e.g., the antenna 119, and/or any device capable of receiving a digital signal 112, 114, and/or 116. The receiver 124 provides the digital video signal 109 to the controller 150. A person of skill in the art knows well the design of the digital receiver 124.

The controller 150 generates image data 132 and control signals 133 by manipulating the digital video signal 109. The display controller 150 provides the image data 132 and control signals 133 to a display device 160. The display 160 includes a pixelated display that has a fixed pixel structure or a CRT. Examples of pixelated displays are active and passive LCD displays, plasma displays (PDP), field emissive displays (FED), electro-luminescent (EL) displays, micro-mirror technology displays, low temperature polysilicon (LTPS) displays, liquid crystal on silicon (LCOS), and the like. A person of reasonable skill in the art should recognize that display 160 may be a television, monitor, projector, personal digital assistant, and other like applications.

The controller 150 may include a variety of components to process the digital video signal 109 for display on the panel 160. The controller and its associated components may be integrated into a monolithic integrated circuit or hardwired using any number of discrete logic and other components. Alternatively, the controller 150 may be a dedicated processor system that includes a microcontroller or a microprocessor (not shown separately).

In an embodiment, the controller 150 may scale the digital video signal 109 for display by the panel 160 using a variety of techniques including pixel replication, spatial and temporal interpolation, digital signal filtering and processing, and the like. In another embodiment, the controller 150 may additionally change the resolution of the digital video signal 109, changing the frame rate and/or pixel rate encoded in the digital video signal 109. Scaling, resolution, frame, and/or pixel rate conversion, and/or color manipulation are not central to this invention and are not discussed in further detail.

Read-only (ROM) and random access (RAM) memories 140 and 142, respectively, are coupled to the display system controller 150 and store bitmaps, FIR filter scaling coefficients, and the like. A person of reasonable skill in the art should recognize that the ROM and RAM memories 140 and 142, respectively, may be of any type or size depending on the application, cost, and other system constraints. A person of reasonable skill in the art should recognize that the ROM and RAM memories 140 and 142, respectively, are optional in the system 100. A person of reasonable skill in the art should recognize that the ROM and RAM memories 140 and 142, respectively, analog receiver 120, and/or digital receiver 124 may be external or internal to the controller 150. RAM memory 142 may be a flash type memory device. Clock 144 controls timing associated with various operations of the controller 150.

Since 1995 Digital View has been providing LCD controller boards, related accessories and engineering services for video display systems, commercial video monitors and other non-consumer displays systems using LCD panels. Offices in USA, UK and Hong Kong with distribution globally.

Watch this 90-second explainer video to learn how MEMC works, what problems it solves and the unique benefits behind the latest advancements in the technology for mobile. #smartphones#mobilephones#display#video@PCarson123@dhurkapic.twitter.com/E8KfTfhT7J— Pixelworks, Inc. (@pixelworksinc) May 8, 2020

Sr. Director Vikas Dhurka: From a capability point of view, the technologies that we provide are agnostic to the screen size and the mechanical design of the display. With the Pixelworks processor, any display could have a visual experience that is far superior than anything else that"s out there.

I think smartphone displays will get more dynamic if you"re following what"s happening in the next round of flagship 120 hertz adaptive frame rate panels - things are going to become more adaptive, not less. So, the whole idea of manually switching and selecting modes, I think, could become outdated.

AThere are numerous Epson LCD Controllers that are specified from -40℃ to +105℃ and therefore fulfill automotive requirements. Please refer to the specific LCD Controller for details.

AThe schematics of evaluation boards are available and can be used as a reference design. Please download evaluation board user manual which contains evaluation board schematics from each LCD Controller products page on vdc.epson.com

AEpson LCD Controllers support generic asynchronous SRAM type interface such as Intel 80, Direct and InDirect 8 and 16-bit bus interfaces. In addition to this, some LCD Controllers supports serial interface. Each product differs in its support so please refer to the specific LCD Controller documentation for details.

AThere are numerous LCD Controllers that have specific 8-bit bus interfaces and others that can be configured using external logic. Please refer to the specific LCD Controller documentation for details.

AEpson LCD Controllers have support for all of the major LCD panel types: STN, CSTN, TFT. Support varies across the product line so please refer to the specific LCD Controller documentation for details.

Q8The LCD TFT panel specification shows an 18-bit data bus, but the LCD controller can store data only as 16bpp (bit-per-pixel). Can I display 16bpp on an LCD TFT panel with 18-bit data bus?

AYes. The TFT panel data bus width is independent of the data stored in memory. The LCD controller will internally expand the number of bits stored the memory to match the LCD panel data bus width. In the above example, 16bpp will be expanded to 18bpp by duplicating the 2 msb"s to the missing 2 lsb"s of the 18-bit value. Please note that the number of colors is still determined by the bit-per-pixel format used to store a pixel in the memory, it will note change by the expansion to match the LCD panel data bus width.

AThe LCD Controller product line provides support for a variety of CPU bus types including both WAIT and no WAIT options. Refer to the specific LCD Controller documentation for details.

AData stored in the frame buffer has an associated bits/pixel (e.g 16bpp). This data is then converted if necessary to match the TFT panel interface width (e.g 16bpp data is converted to 18-bit data width). This data is then transferred one pixel/clock as shown in the following diagram.

AThe input clock frequency requirements are all included in the Hardware Specification for each part and differ across the product line. If an LCD Controller has a built-in PLL, then typically a lower input clock source is sufficient as all internal clocks are driven by the PLL. If an LCD Controller does not contain a PLL, then a higher frequency input clock source is typically required as all of the internal clocks are generated from this single source. Please refer to the specific LCD Controller documentation for details.

AThe recommended replacement parts are the S1D13700 and the S1D13709, however specific project requirements need to be considered as another LCD Controller may be more suitable.

AThe maximum pixel clock is determined by the LCD panel itself and not the LCD Controller. Please refer to the specific LCD panel documentation for details. If the LCD Controller supports the display resolution, then most likely there will be numerous Pixel clock frequencies to choose from depending on the desired refresh rate.

AEmbedded / internal LCD Controllers can be quite limiting with respect to display resolution, power down modes, color depths, available bandwidth and specialized features. They are typically included in a processor design as simply one of many peripherals and therefore no special care is taken in the design or feature set. Using an external LCD Controller is usually required to alleviate one of the above mentioned limitations. Higher resolutions are supported, overall system power can be reduced by allowing the processor to "sleep" while the external LCD Controller maintains display refresh. Extensive display orientated features can be realized such as acceleration, windowing, higher color depths, simultaneous displays, etc.

AMany Epson LCD Controllers include sample code, APIs, configuration tools, and sample Linux drivers. Please visit the product page for each LCDC for a detailed list..

ANo. In all of our controllers that support CMOS/CCD camera"s, the camera data is piped to the frame buffer. A region (Picture in Picture) within the overall frame buffer is configured for the camera data. The display refresh circuitry reads this data and displays it without any intervention from the host CPU.

AWe support cameras with digital output only, including cameras with output complying with ITU-R-656. Depending on the specific controller we support multiple data formats: YUV 4:2:2, JPEG. Please refer to the spefic product documentation for details.

AYes. We have several products that support multiple LCD panels. For example, the S1D13719 can support 2 active panels with the following interfaces: RGB, Serial, Parallel.

AIf a clock input is not used in a design, it should be connected to ground, either directly or through a resistor. If the LCD controller has a crystal port and it is not used, then the input pin should be connected to ground, either directly or through a resistor, and the output pin should be left not connected.

ANo, ceramic resonators can not be used instead of the crystals. The internal oscillator in the LCD controller, is not designed to work with a ceramic resonator.

ANo. The inputs do not tolerate voltages higher than the IO supply voltage, so if the IO voltage is 3.3V, the LCD controller will not tolerate 5V signals. Please refer to the absolute maximum ratings for each product.

Q25If a block inside the LCD controller is not used in my design, can I leave the power pins supplying that block unconnected? For example I am using S1D13719 and I am not using the SD Card interface, so what shall I do with SIOVDD pins?

AAll power pins must be connected to a power supply in our LCD controllers, no power pin should be left not connected. Even if a particular block in the LCD controllers is not used, the power pin for that block can not be left floating, they should be connected to a power supply.

ANo. Our LCD controllers will be in power save mode at power up and the memory can not be accessed. You must put the LCD controller in normal operation before being able to access the memory.

AThe Epson web site has API, sample code and reference drivers for all controllers in the marketing channel. The sample code offered may vary depending on initial software requests. Sample code is updated from time to time so check back to the web site for the latest versions.

AWhile we make every effort to support all our controllers across a variety of platforms, due to limited resources it is impossible to provide a custom driver for every controller and operating system platform combination. If the driver you require is not available, contact us and we can suggest the best starting point for developing a driver to suit your needs.

AThe APIs for some LCD controllers include a simple graphics library intended for demonstration and example purposes. There are many excellent third party libraries providing this functionality.

AThe S1D13xxxCFG utility is a tool to assist with configuring Epson display controllers for use with your specific hardware. After the fields of the CFG utility are filled with your specific hardware configuration, the CFG utility can generate a file containing register values explicit to your needs. If the Epson controller is installed in the machine the CFG utility is run on then the CFG utility can also be used to directly tweak register settings. This is particularly useful for obtaining precise panel configuration values. In addition to this, simple to use type panel setting tool is available for some LCD Controllers.

Q32We have been using CHIP-A from Epson but in the future we will be using CHIP-B. What changes, if any, do I have to make changes to my software to support the new controller?

AWhile many of our controllers support similar features or register layouts it is not usually possible to continue using your existing code base without some modification. The extent of the changes is dependent on the complexity of the controller and the differences between the old and new controllers. This is something that needs to be examined on a case by case basis.

The controller line address offset (stride) is not the same as the line address offset your graphics routine is using. Image appears twice (on the top and the bottom of the display) or fuzzy. Likely cause is the controller is set to 16bpp and you are drawing at 8bpp.