tft lcd 氇媹韯?0 made in china

f ^ 45926 7 A7 ______B7 ____ 五、發明說明（1 ) 發明背景： 1 .發明領域： 本發明係關於一種主動矩陣型式半導體顯示裝置之驅 動電路。本發明亦關於具有驅動電路之半導體顯示裝置。 2 .相關技藝之敘述： 近年來，已快速地發展一種技術，用於製造具有形成 在便宜的玻璃基體上之半導體薄膜的半導體裝置，例如薄 膜電晶體（TFT) >原因是對於主動矩陣型式半導體顯 示裝置（特別是主動矩陣型式液晶顯示裝置）之需求增加 〇 在主動矩陣型式液晶顯示裝置中，對於擺設在矩陣中 之數十至百萬個圖像設置一 TFT，且藉著TFT之開關 功能而控制電荷進出各圖像電極。 特別是，隨著顯示裝置在解析度及圖像品質的改良， 已注意到主動矩陣型式液晶顯示裝置，具有可以處理數位 視頻資料之數位驅動電路。在包括數位驅動電路之半導體 顯示裝置的源信號線側驅動電路中，從外側供給之數位視 頻資料依序地被一閂鎖電路保留一段短的時間，根據來自 移位暫存器之時間信號。且在資料被轉換成類比信號（階 、 度電壓）之後，信號被供給至對應的圖像TFT 〇當使用 數位驅動電路時，可以實現所謂直線順序驅動，其中同時 驅動一直線之圖像TFT。 在數位驅動電路中，根據來自移位暫存器之時間信號 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） <锦先閲讀背面之注意事項再填寫本頁}f ^ 45926 7 A7 ______B7 ____ V. Description of the invention (1) Background of the invention: 1. Field of the invention: The present invention relates to a driving circuit for an active matrix type semiconductor display device. The invention also relates to a semiconductor display device having a driving circuit. 2. Description of related technologies: In recent years, a technology has been rapidly developed for manufacturing semiconductor devices having a semiconductor thin film formed on an inexpensive glass substrate, such as a thin film transistor (TFT) > The reason is for the active matrix type The demand for semiconductor display devices (especially active matrix type liquid crystal display devices) has increased. In active matrix type liquid crystal display devices, a TFT is provided for tens to millions of images arranged in a matrix, and a TFT switch is used. Function to control charge in and out of each image electrode. In particular, with the improvement in resolution and image quality of display devices, it has been noted that active matrix liquid crystal display devices have digital drive circuits that can process digital video data. In a source signal line side driving circuit of a semiconductor display device including a digital driving circuit, digital video data supplied from the outside is sequentially retained by a latch circuit for a short period of time, based on the time signal from the shift register. And after the data is converted into analog signals (step, degree voltage), the signals are supplied to the corresponding image TFTs. When a digital drive circuit is used, the so-called linear sequential drive can be realized, in which linear image TFTs are driven simultaneously. In the digital drive circuit, according to the time signal from the shift register, the paper size applies the Chinese National Standard (CNS) A4 (210 X 297 mm) < Jinxian read the precautions on the back before filling in this page}

-lull — — « I I II 經濟部智慧財產局貝工消费合作社印製 A7 B7 459267 五、發明說明（2 ) {諳先閲讀背面之生意事項再填寫本頁) ，決定邏輯電路、D/A轉換電路之操作時間。各具有大 的負載容量之許多電路與元件被連接至一信號線，時間信 號從移位暫存器供給至此信號線。於是，會發生一情形， 來自移位暫存器之時間信號會在路上產生“鈍化”。對此 的其中一個對策，嚐試使來自移位暫存器之時間信號通過 一緩衝器電路以消除•鈍化”。 如果緩衝器電路之電流容量很小，緩衝作用是無意義 的。所以，需要具有大到某一程度的電流容量之緩衝器。 在使用薄膜電晶體形成具有大的電流容量之緩衝器的情形 中，需要具有大的電流容量亦即大的通道寬度之T F T。 然而，在具有大的通道寬度之TF T中，零件中會發生結 晶的起伏，結果，對於各TF T發生臨界電壓的起伏。於 是，無可避免地在由許多T F T構件的緩衝器之特性中亦 會發生起伏。於是，存在具有對於各信號線之特性起伏0¾ 緩衝器，且此特性起伏會導致施加至圖像矩陣電路之電壓 ______.··.·.+ - 的起伏》如此會引起顯示裝置整體的禪示模糊（顯示不均 勻）。 經濟部智慧財產局貝工消f合作社印製 此外，如果TFT之尺寸（通道寬度）太大，只有 TF T之中央部份作用爲一通道，且其尾端並不會作用爲 通道。在此情形中，加速TFT的變差。 此外，當TFT的尺寸很大時，TFT之自動加熱產 生會變大，其有時會導致臨界電壓的改變或變差° 同樣在閘信號線側驅動電路中，根據來自移位暫存器 之時間信號，一掃描信號被依序地供給至一閘信號線（掃 本紙張疋度.通用中囡國家標準（CNS>A4規格（210 X 297公* ) 459267 A7 B7 ___ 五、發明說明（3 ) 描線）。在執行直線依序驅動的數位驅動電路中，必須驅 動對於連接至一掃描線的一直線之全部圖像T F T，且連 接至一掃描線之負載容量很大。於是，在閘信號線側驅動 電路中，需要藉著使來自移位暫存器之時間信號通過一緩 衝器電路等等而消除“鈍化”。而且在此情形中，由於需 要具有大的電流容量之緩衝器，會發生上述問題。特別是 ，閘信號線之緩衝器必須驅動圖像矩陣電路中一直線的全 部連接T F T，所以緩衝器之特性起伏會造成明顯的圖像 不均勻。這是當需要具有高的精細度/高的解析度之顯示 裝置時的其中一個最嚴重的問題。 發明節要： 做成本發明以克服前述問題，且本發明之目的在於提 供一種半導體顯示裝置•其可消除圖像模糊（顯示不均勻 )，且可得到具有高的精細度/高的解析度之良好圖像。 依據執行本發明的一個模式，在半導體顯示裝置之驅 動電路中，作爲構成設於移位暫存器電路與源信號線側驅 動電路的閂鎖電路之間的緩衝器電路之T F T，並沒有使 用具有大的尺寸（.通道寬度）的TFT，而是使用許多 T、F T ·各具有小的尺寸且彼此並聯地連接》此外，作爲 、 構成設於移位暫存器電路與閘信號線側驅動電路的閘信號 之間的緩衝器電路之T F Τ，並沒有使用具有大的尺寸（ 通道寬度）的TF Τ，而是使用許多TF Τ，各具有小的 尺寸且彼此並聯地連接。在此兩種情形中，許多緩衝器電 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公荣） <請先閲讀背面之注意事項再填寫本頁) ό 裝 --------訂-------- 經濟部智慧財產局貝工消费合作社印製 4 5926 7 經濟部智慧財產局貝工消费合作社印製 五、發明說明（4) 路被並聯地連接，以構件驅動電路中的緩衝器電路部份。 藉著如此做，可以減小緩衝器電路之特性起伏，而確保其 電流容量。 以下將敘述本發明之構造。 依據本發明的一個觀點，提供一種半導體顯示裝置之 驅動電路，包含：一源信號線側驅動電路；及一閘信號線 側驅動電路，其中閘信號線側驅動電路包括一緩衝器電路 ，此緩衝器電路緩衝來自一移位暫存器電路之時間信號， 且包括許多反相器電路，各反相器電路是由彼此並聯地連 接的許多反相器構成。藉此可達到上述目的。 依據本發明的另一個觀點，提供一種半導體顯示裝置 之驅動電路，包含：一源信號線側驅動電路；及一閘信號 線側驅動電路，其中源信號線側驅動電路包括一緩衝器電 路，此緩衝器電路緩衝來自一移位暫存器電路之時間信號 ，且包括許多反相器電路，各反祖器電路是由彼此並聯地 連接的許多反相器構成。藉此可達到上述目的。 依據本發明的更另外一個觀點，提供一種半導體顯示 裝置之驅動電路，包含：一源信號線側驅動電路；及一閘 信號線側驅動電路•其中源信號線側驅動電路包括一緩衝 器電路，此緩衝器電路緩衝來自一移位暫存器電路之時間 信號，且包括許多反相器電路，各反相器電路是由彼此並 聯地連接的許多反相器構成，且其中閘信號線側驅動電路 包括一緩衝器電路，此緩衝器電路緩衝來自一移位暫存器 電路之時間信號，且包括許多反相器電路，各反相器電路 <靖先閲讀背面之注意事項再填寫本頁) 裝 n n n n^SJ· n n-lull — — «II II Printed A7 B7 459267 by the Shellfish Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economy V. Invention Description (2) {谙 Read the business matters on the back before filling this page), decide the logic circuit, D / A conversion Operating time of the circuit. Many circuits and components each having a large load capacity are connected to a signal line, and a time signal is supplied from the shift register to this signal line. Then, there will be a situation where the time signal from the shift register will be “passivated” on the road. As one of the countermeasures, try to pass the time signal from the shift register through a buffer circuit to eliminate passivation. "If the current capacity of the buffer circuit is small, the buffering effect is meaningless. Therefore, it is necessary to have A buffer with a large current capacity. In the case where a thin film transistor is used to form a buffer with a large current capacity, a TFT having a large current capacity, that is, a large channel width is required. In the TF T of the channel width, crystal fluctuations occur in the parts, and as a result, fluctuations in the threshold voltage occur for each TF T. Therefore, fluctuations in the characteristics of the buffer composed of many TFTs inevitably occur. Therefore, there is a buffer having a characteristic fluctuation of each signal line, and this characteristic fluctuation will cause the voltage applied to the image matrix circuit to fluctuate ______. ····. +-This will cause the Zen of the display device as a whole. Blurred (uneven display). Printed by Cooperative, Intellectual Property Bureau, Ministry of Economic Affairs. In addition, if the TFT size (channel width) is too large, only The central part of TF T functions as a channel, and its tail end does not function as a channel. In this case, the deterioration of the TFT is accelerated. In addition, when the size of the TFT is large, the automatic heating of the TFT will change. Large, it sometimes causes the threshold voltage to change or worsen. Also in the gate signal line side drive circuit, according to the time signal from the shift register, a scan signal is sequentially supplied to a gate signal line ( Scanning paper size. General Chinese National Standard (CNS > A4 specification (210 X 297 male *) 459267 A7 B7 ___ V. Description of the invention (3) Draw line). In a digital drive circuit that performs straight-line sequential driving, it is necessary to Drives all the image TFTs connected to a scan line for a straight line, and the load capacity connected to a scan line is large. Therefore, in the gate signal line side drive circuit, it is necessary to adjust the time from the shift register. The signal is “passivated” through a buffer circuit, etc. Also, in this case, the above-mentioned problem occurs because a buffer having a large current capacity is required. In particular, the buffer of the gate signal line must be driven All the linear TFTs in the image matrix circuit are connected, so the fluctuation of the characteristics of the buffer will cause obvious image unevenness. This is one of the most serious when a display device with high fineness / high resolution is needed. Problem Summary of the Invention: The invention is made to overcome the aforementioned problems, and an object of the present invention is to provide a semiconductor display device which can eliminate image blur (uneven display) and obtain high resolution / high resolution. According to one mode for carrying out the present invention, in a driving circuit of a semiconductor display device, a buffer circuit is formed between a shift register circuit and a latch circuit of a driving circuit on a source signal line side. The TFT does not use a TFT with a large size (. Channel width), but uses a large number of T and FTs. Each has a small size and is connected in parallel with each other. In addition, it is provided as a structure in a shift register circuit. The TF of the buffer circuit between the gate signal and the gate signal of the driver circuit on the gate signal line side does not use a TF with a large size (channel width). , But the use of a number of TF Τ, each having a small size and parallel to each other. In both cases, many buffer paper sizes are applicable to China National Standard (CNS) A4 specifications (210 X 297 Gongrong) < Please read the precautions on the back before filling out this page) ---- Order -------- Printed by the Shellfish Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 5926 7 Printed by the Shellfish Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (4) The roads are connected in parallel To drive the buffer circuit part of the circuit. By doing so, it is possible to reduce the characteristic fluctuation of the snubber circuit and ensure its current capacity. The structure of the present invention will be described below. According to an aspect of the present invention, a driving circuit for a semiconductor display device is provided, including: a source signal line side driving circuit; and a gate signal line side driving circuit, wherein the gate signal line side driving circuit includes a buffer circuit, and the buffer The inverter circuit buffers the time signal from a shift register circuit, and includes a plurality of inverter circuits. Each inverter circuit is composed of a plurality of inverters connected in parallel with each other. This can achieve the above purpose. According to another aspect of the present invention, a driving circuit for a semiconductor display device is provided, including: a source signal line side driving circuit; and a gate signal line side driving circuit, wherein the source signal line side driving circuit includes a buffer circuit, and The buffer circuit buffers the time signal from a shift register circuit and includes a plurality of inverter circuits. Each inverter circuit is composed of a plurality of inverters connected in parallel with each other. This can achieve the above purpose. According to still another aspect of the present invention, a driving circuit for a semiconductor display device is provided, which includes: a source signal line side driving circuit; and a gate signal line side driving circuit. The source signal line side driving circuit includes a buffer circuit. The buffer circuit buffers the time signal from a shift register circuit and includes a plurality of inverter circuits. Each inverter circuit is composed of a plurality of inverters connected in parallel with each other, and the gate signal line side is driven. The circuit includes a buffer circuit, which buffers the time signal from a shift register circuit, and includes many inverter circuits. Each inverter circuit < read the precautions on the back before filling this page ) Install nnnn ^ SJ · nn

.459267 M __B7___ 五、發明說明（10 ) 閂鎖電路（1)1 04中的數位信號同時被傳送至閂鎖電 路（2 ) 1 0 5並被寫入。 在完成將數位視頻資料傳送至閂鎖電路（2 ) 1 0 5 的閂鎖電路（1 ) 1 0 4中，藉著來自移位暫存器電路 1 0 2的時間信號，再度依序地執行從數位視頻資料驅動 電路供給的數位視頻資料之寫入。 於此第二單線周期期間，與第二單線周期之開始同步 被傳送至閂鎖電路（2 )的數位視頻資料，被選定電路（ 1)106依序地選定。選定電路之細節揭示於本案受讓 人之1 9 9 7年十月一日所申請的日本專利第He.i 9 —2 8 6 0 9 8號中，其可作爲參考》包括說明書、申請 專利範圍、圖彤與節要之日本專利第He i 9 — 2 8 6 0 9 8號的整體揭示在這裡作爲參考。 四位元數位視頻資料從選定電路所選定的閂鎖電路被 供給至位準移位電路1 0 7。由位準移位電路1 0 7來升 高數位視頻資料之電壓位準，且資料被供給至D/A轉換 電路1 0 8。可參考揭示本案受讓人於1 9 9 7年十一月 27曰所申請的日本專利第He i 9 — 344351號 及1997年十二.月19日所申請的日本專利第He i 9、一 3 6 5 0 5 4號所揭示的D/A轉換電路之細節。在 \ 這裡係整體地參考包括說明書、申請專利範圍、圖形與節 要的上述日本專利申請案。 D/A轉換電路1 0 8將四位元的數位視頻資料轉換 成一類比信號（階度電壓），其依序地被供給至由選定電 本紙張尺度適用中國國家標準（CNS>A4規格（210 X 297公« ) (诗先閱讀背面之注意事項再填寫本頁} 裝 !1 訂 *1! 經濟部智慧財產局具工消f合作社印製 -To 五、發明說明（11) 路（2 ) 1 0 9所選定的源信號線。供給至源信號線之類 比信號被供給至連接到源信號線之圖素矩陣電路1 1 6的 圖素TFT之源區。 在閘信號線側驅動電路A 1 1 2中，來自移位暫存器. 1 1 3之時間信號被供給至一緩衝器電路1 1 4，且被供 給至一對應的閘信號線（掃描線）》—線的圖素TFT之 閘電極被連接至閘信號線，且一線之全部圖素T F T必須 同時被打開，所以使用具有大的電流容量之緩衝器電路 114。 以此方式，藉著來自閘信號線側移位暫存器之掃描信 號，而執行對應的T F T之開關，且來自源信號線側驅動 電路之類比信號（階度電壓）被供給至圖素T F T，使得 驅動液晶分子。 參考數字1 1 1代表源信號線側驅動電路B，且其構 造是與源信號線側驅動電路A 1 0 1相同。源信號線側驅 動電路B 1 1 1將一圖像信號供給至偶數的源信號線。 參考數字1 1 0代表數位視頻資料驅動電路。數位視 頻資料驅動電路1 1 0是一電路，用於減小從外側輸入的 數位視頻資料之頻率，約1 /m的比例。藉著分割數位視 頻資料，驅動電路之操作所需的信號之頻率亦可被減小爲 約 1 / m。 這裡，主要參見圖2，將敘述此實施例之數位視頻資 料驅動電路1 1 0。附帶一提，由本案受讓人於1 9 9 7 年十二月8日所申請的日本專利第He i 9 — 本紙張尺度，適用中國國家標準（CNS)A4規格（210 X 297公S ) ("if先閲讀背面之注意事項再填寫本頁).459267 M __B7___ 5. Description of the Invention (10) The digital signals in the latch circuit (1) 104 are simultaneously transmitted to the latch circuit (2) 105 and written. In the latch circuit (1) 1 0 4 which finishes transmitting the digital video data to the latch circuit (2) 1 0 5 by the time signal from the shift register circuit 1 02, it is sequentially executed again. Writing of digital video data supplied from a digital video data driving circuit. During this second single-line cycle, the digital video data transmitted to the latch circuit (2) in synchronization with the start of the second single-line cycle is sequentially selected by the selection circuit (1) 106. The details of the selected circuit are disclosed in Japanese Patent No. He.i 9-2 8 6 0 9 8 filed by the assignee of this case on October 1, 997, which can be used as a reference, including the specification and patent application. The entire disclosure of Japanese Patent No. Hei 9-2 608 0 98 of the scope, drawings, and summary is incorporated herein by reference. Four-bit digital video data is supplied from the latch circuit selected by the selection circuit to the level shift circuit 107. The voltage shift level of the digital video data is raised by the level shift circuit 107, and the data is supplied to the D / A conversion circuit 108. Reference may be made to the disclosure of Japanese Patent No. Hei 9-344351 filed by the assignee of this case on November 27, 1997 and Japanese Patent No. Hei 9,1 filed on December 19, 1997. Details of the D / A conversion circuit disclosed in No. 3 6 5 0 5 4. \ Here is a complete reference to the above Japanese patent application including the description, patent application scope, figures and excerpts. The D / A conversion circuit 108 converts the four-bit digital video data into an analog signal (gradient voltage), which is sequentially supplied to the selected paper size and applies the Chinese national standard (CNS > A4 specification (210 X 297 公 «) (Read the notes on the back of the poem before filling out this page} Pack! 1 Order * 1! Printed by the Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs-To V. Description of Invention (11) Road (2) The selected source signal line 1 0 9. The analog signal supplied to the source signal line is supplied to the source region of the pixel TFT of the pixel matrix circuit 1 1 6 connected to the source signal line. The driving circuit A is on the gate signal line side. In 1 1 2, the time signal from the shift register. 1 1 3 is supplied to a buffer circuit 1 1 4 and is supplied to a corresponding gate signal line (scanning line). The gate electrode is connected to the gate signal line, and all the pixel TFTs of the first line must be turned on at the same time, so a buffer circuit 114 having a large current capacity is used. In this way, by shifting from the gate signal line side to temporarily store The scanning signal of the controller, and the corresponding TFT switch is executed, and The analog signal (step voltage) of the signal line side driving circuit is supplied to the pixel TFT to drive the liquid crystal molecules. Reference numeral 1 1 1 represents the source signal line side driving circuit B, and its structure is the same as that of the source signal line side driving circuit. A 1 0 1 is the same. The source signal line side drive circuit B 1 1 1 supplies an image signal to an even number of source signal lines. The reference number 1 1 0 represents a digital video data drive circuit. The digital video data drive circuit 1 1 0 is A circuit for reducing the frequency of digital video data input from the outside by a ratio of about 1 / m. By dividing the digital video data, the frequency of signals required for the operation of the driving circuit can also be reduced to about 1 / m m. Here, referring mainly to FIG. 2, the digital video data driving circuit 1 1 0 of this embodiment will be described. Incidentally, the Japanese patent No. 1 filed by the assignee of this case on December 8, 1997 He i 9 — This paper size applies to China National Standard (CNS) A4 (210 X 297 male S) ("if read the precautions on the back before filling this page)

· I ! I I 訂· I I ---- 經濟部智慧財產局異工消费合作社印製 A7 B7 4-5926 7 五、發明說明（12 ) t 閲 讀 背 面 之 注 意 事 項 再 填 % 本 頁 3 5 6 2 3 8號，揭示數位視頻資料驅動電路被集積地形 成在相同基體上作爲圖素矩陣電路及其它的驅動電路。上 述專利揭示數位視頻資料驅動電路之操作的細節，可被參 考以瞭解此實施例之數位視頻資料驅動電路的操作。包括 說明書、申請專利範圍、圖形與節要之日本專利第H e i 9 一 3 5 6 2 3 8號的整個揭示在這作爲參考^ 在圖2中，參考數字2 0 1代表一同步計數器，且輸 入一時鐘信號（c k)及一重置脈衝（重置）。在此實施 例中，從外側供給的8 ΟΜΗ z之數位視頻資料被分成8 段，所以產生1 ΟΜΗζ的數位視頻資料。於是，十六個 D正反器2 0 2被連接成如圖2所示。由數位視頻資料驅 動電路110所產生的1ΟΜΗζ之數位視頻資料被供給 至閂鎖電路（1 ) 1 0 4，如上所述。 經濟部智慧財產局貝工消费合作社印製 再度參見圖1，將敘述閘信號線側驅動電路之操作。 參考數字1 1 2代表閘信號線側驅動電路Α。閘信號線側 驅動電路A 1 1 2包括移位暫存器電路1 1 3及緩衝器電 路1 1 4。移位暫存器電路1 1 3將一時間信號供給至緩 衝器電路1 1 4。緩衝器電路1 1 4緩衝來自移位暫存器 電路1 1 3之時間信號，並將它供給至閘信號線（掃描線 參考數字1 1 5代表閘信號線側驅動電路B，且具有 與閘信號線側驅動電路A 1 1 2相同的構造。在此實施例 中，以此方式將閘信號線側驅動電路設在圖素矩陣電路 1 .1 6的兩側，且操作此兩個閘信號線側驅動電路，使得 本紙張尺度適用中國國家標準（CNS>A4規格（210 X 297公爱） A7 B7 45926 7 五、發明說明（13 ) 此實施例即使在其中一個沒有操作之情形亦能操作。 圖素矩陣電路1 1 6具有此一構造，圖素TFT擺設 成矩陣，在水平與垂直上的數目爲1 9 2 Ο X 1 0 8 0。 一銀幕（一圖框）是藉著以掃描線之數目來重覆前述. 操作而形成。在此實施例的主動矩陣型式液晶顯示裝置中 ，執行每秒6 0個圖框之圖像更新。 這裡，此實施例的一部份（上方部份）移位暫存器電 路1 0 2與緩衝器電路1 0 3的電路圖將表示於圖3中。 圖3指出構成移位暫存器電路1 0 2之正反器（F F )電 路102’及構成緩衝器電路103的一部份緩衝器電路 10 3"。 在此實施例中，由240個正反器電路1021來構 成移位暫存器電路1 0 2。正反器電路1 0 2’包括反相 器30 1至304 »參考字元ck代表一時鐘信號。參考 字元L R代表一掃描方向改變信號。當信號L R爲高時， 一啓始脈衝（S Ρ )被供給至移位暫存器電路1 0 2的最 左邊正反器電路102’ ，且正反器電路102’從左至 右轉移信號。當信號LR爲低時，一啓始脈衝（S.P )被 供給至最右邊正反器電路（未示），且正反器電路 1、0 2 ’從右至左轉移信號。 以下將說明信號L R爲高時之情形作爲例子’亦即從 左萆右操作移位暫存器電路1 0 2之正反器電路。 —啓動脈衝（S Ρ )被輸入反相器3 0 1中。當啓動 脈衝被輸入反相器3 0 1中時，反相器3 0 1與時鐘信號 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） I-------------裝 -----—訂- ------ (骑先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消t合作社印製 45926 7 A7 B7___ 五、發明說明（14) (错先閱讀背面之注意事項再填寫本頁) (c k)及反相時鐘信號（反相c k)同步地操作，且輸 出輸入信號之反相信號》由於信號LR (高）被輸入於反 相器3 0 2中*反相器3 0 2接收來自反相器3 0 1之信 號，並輸出其反相信號》反相器3 0 4接收來自反相器 302之信號，並輸出其反相信號。由於信號LR (高） 被輸入於反相器3 0 3中，它不會操作。以此方式，正反 器電路102’將一時間信號輸出至NAND電路305 〇 來自移位暫存器電路102(正反器電路102’ ) 之時間信號通過NAND電路3 0 5，並被輸入至一部份 的緩衝器電路10 3’ 。在此實施例中，一部份的緩衝器 電路1 0 3 ’包括五，個反相器306至3 10。雖然在此 實施例中一部份的緩衝器電路103’包括五個反相器， 在本發明中反相器的數目並不限於此，但可包括小於五或 大於五之數目的反相器。 經濟部智慧財產局貝工消费合作社印製 此五個反相器3 0 6至3 1 0分別由具有不同尺寸（ 通道寬度）的TFT構成。在此實施例中，由各具有30 之通道寬度的TFT構成反相器3 0 6，3 0 7與 308。由各具有100#m之通道寬度的TFT構成反 相、器3 0 9與3 1 0 *對於構成這些反相器之TFT的尺 寸，可經由模擬而使用最佳尺寸*此外，可依據半導體顯 示裝置之圖素數目等等來決定T F T之最佳尺寸。 這裡，將使用反相器3 0 7作爲例子來說明。圖4是 反相器3 0 7的電路圖。反相器3 0 7是由六個P通道 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公* ) · If · ! 45926 7 A7 B7 五、發明說明（15) TFT及六個N通道TFT所構成。各TFT之通道寬度 爲3 0 。附帶一提，這些TFT之通道寬度被做成 I 0 0 //m或更小（最好是9 0 或更小）是合適的。 如圖4所示，反相器3 0 7具有一構造，兩個反相器 電路彼.此並聯地連接，各反相器電路是由兩個電路構成， 其中一個電路三個Ρ通道TFT彼此串聯地連接（在電路 中使用三閘TFT)，另一個電路三個N通道TFT彼此 串聯地連接（在電路中使用三閘TFT)。與此類似，當 組合各具有小的通道寬度（此實施例中爲3 0 #m)之許 多線的T F T時，與由各具有大的通道寬度之T F T所構 成的反相器之情形相比，可消除TF T中的起伏。此外， 可避免由於大的通道寬度所引起的熱產生及變差。 接著，將參見圖5。圖5是一電路圖*指出此實施例 之閘信號線側驅動電路A 1 1 2的緩衝器電路1 1 4及一 部份（上方部份）的移位暫存器電路1 1 3，且指出構成 移位暫存器電路1 1 3的正反器電路1 1, 3’及構成緩衝 器電路114的一部份緩衝器電路114’ 。 在此實施例中，移位暫存器電路1 1 3是由1080 個正反器電路11. 3’所構成。正反器電路11 3’包括 反、相器50 1至504。參考字元ck代表一時鐘信號》 參考字元L R代表一掃描方向改變信號，且當信號L R爲 高時，一啓動脈衝（S P )被供給至移位暫存器電路 II 3之最左邊的正反器電路11 3’ .，且當信號LR爲 低時，一啓動脈衝（S P )被供給至最右邊的正反器電路 本紙張尺度適用中國國家標準（CNS)A4規格<210 * 297公爱> (诗先閱讀背面之注意事項再填窝本頁) N 裝--------訂--------.AUI. 經濟部智慧財產局貝工消費合作社印製 459267 A7 B7 五、發明說明（16 ) (未示）β (骑先閱讀背面之注意事項再填寫本頁) S於移位暫存器電路113的操作是與源信號線側驅 動電路之移位暫存器電路102相同，所以省略其說明。’ 籴自移位暫存器電路1. 1 3 (正反器電路1 1 3’ ） 之時間信號通過NAND電路5 0 5，且被供給至一部份 的緩衝器電路114，。此部份的緩衝器電路114’包 括三個反相器5 0 6至5 0 8。在此實施例中，雖然一部 份的緩器電路114·包括三個反相器，在本發明中反 相器的數目並不限於此，亦可包括數目小於三或大於三之 反相器。 此三個反相器5 0 6至5 0 8是由各具有9 0 的 通道寬，度之T FT構成f對於構成這些反相器的T F T之 尺寸，可經由模擬而選定最佳尺寸》此外，可依據半導體 顯示裝置之圖素數目等等來決定TF T之最隹尺寸》 圖6是反相器5 0 8的電路圖。反相器5 0 8是由八 個P通道TFT及八個N通道TFT構成•各TFT之通 道寬度爲9 0 。這些TF T之通道寬度被做成1 〇 0 或更小（最好是9 0 或更小）是合適的。 經濟部智慧財產局貝工消费合作社印製 如圖6所示，.兩個電路彼此並聯地連接’各電路是由 兩個P通道TFT彼此串聯地連接而構成（實際上使用雙 、 閘丁FT)。此外’兩個電路彼此並聯地連接’各電路是 由兩個N通道T F T彼此串聯地連接而構成（實際上使用 雙間TFT)。反相器5 0 8是由這些電路構成β與此類 似，當組合各具有小的通道寬度之許多線的T F 丁時，與 -iy - 本纸張尺度適用中國國家標準（CNS>A4規格（210 X 297公^ ) 經濟部智慧財產局具工消费合作社印製 d 5926 7 · a? __ __ B7____ 五、發明說明（17) 由各具有大的通道寬度之T F T所構成的反相器之情形相 比，可消除TFT中的起伏，並確保電流容量。此外，可 避免由於大的通道寬度所引起的熱產生及變差。 圖7爲圖4所示的反相器3 0 7之電路圖。在圖7中 ，參考數字7 0 1與7 0 2代表加入Ν型雜質的半導體活 性層。參考數字7 0 3與7 0 4代表加入Ρ型雜質的半導 體活性層》參考數字7 0 5代表一閘電極電線，且在此實 施例中使用包括2重量百分比的Sc (銃）之A 1 (鋁） 。參考數字7 0 8至7 1 1代表第二電線且在此實施例 中使用鋁。參考數字7 1 2代表存在於與閘電極電線相同 層中的電線。典型地由7 1 3所代表的虛線部份爲閘電極 被連接至第二電線的部份，或半導體活性層被連接至第二 電線的部份* 參考數字706代表GND，707代表VddH ( 電源），712代表OUT (輸出），且714代表IN (輸入）。 圖形中，假設具有相同圖案的電線存在於相同的電線 層中。由圖形中之虛線所表示的部份指出由上電線所隱藏 的下方電線之形狀。 、 在圖7所示的反相器307中，雖然在相同的半導體 層上形成三個P通道TFT及三個N通道TFT，亦可以 採用一構造，三個獨立的P通道TF T與三個獨立的N通 道T F T形成在獨立的半導體層上，且被金屬電線或經由 接點而彼此連接。然而，由於反相器3 0 7的面積可被做 本紙張尺度译用中國國家標準（CNS)A4規格<210 297公釐） — —裝 - ------訂·---1 {锖先閱讀背面之注意事項再填莴本頁) d5926 7 五、發明說明（18) 得更小，此實施例的構造是較佳的》 接著，將參見圖8。圖8爲圖6所示的反相器5 0 8 之電路圖案。圖8中，除了反相器5 0 8外，總共指出四 個反相器。 在圖8中，參考數字8 0 1至8 0 8代表加入P型雜 質的半導體活性層》參考數字8 0 9至8 1 6代表加入N 型雜質的半導體活性層。參考數字81 7至8 2 4代表閘 電極電線，且在此實施例中使用包括2重量百分比的S c (銃）之A 1 (鋁）。參考數字8 2 5至8 2 8代表存在 於與閘電極電線相同層中的電線。參考數字8 2 9至 8 3 5代表第二電線，且在此i施例中使用鋁。典型地由 8 3 6所代表的虛線部份爲閘電極被連接至第二電線的部 份，或半導體活性層被連接至第二電線的部份。 參考數字829代表VddH(高壓電源），832 代表GND，且833代表VddL (低壓電源）。附帶 一提，各參考字元I N1至I N4代表輸入，且各 OUT1至OUT4代表輸出》 圖形中，具有相同圖案的電線是由相同的材料製成， 且存在於相同的電線層中。由圖形中之虛線所表示的部份 指出由上電線所隱藏的下方電線之形狀》 這裡，將敘述包括此實施例之驅動電路的主動矩陣型 式液晶顯示裝置之製造方法•附帶一提，以下所敘述的製 造方法是一種實現本發明之製造方法，藉由其它的製造方 法亦可以實現本發明之主動矩陣型式液晶顯示裝置。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ί"ΐί先閱讀背面之注意事項再填莴本頁} ""裝-----—訂 —----^lw_. 經濟部嘴慧財產局貝工消f合作社印製 45926 7 A7 45926 7 A7 經濟部智慧財產局員工消费合作社印製 B7 五、發明說明（19 ) 這裡，參見圖9至1 2將敘述一例子，其中許多 T F T形成在一具有絕緣表面之基體上，且單石地形成圖 素矩陣電路、驅動電路、邏輯電路等等。在此實施例中， 將指出一狀態，其中同時形成圖素矩陣電路的一圖素承 CMO S電路作爲其它電路（驅動電路、邏輯電路等等） 的基本電路。在此實施例中，雖然將敘述對於各Ρ通道 TFT與Ν通道TFT各包括一閘極之情形的製造步驟， 以相同的方式亦可以製造各具有許多閘電極例如雙閘型或 三閘型TFT之TFT的CMOS電路。 以下將參見圖9 A至9 D。首先，製備一石英基體作 爲具有絕緣表面之.基體。不使用石英基體，亦可使用其上 形成熱氧化膜之矽基體。此外，可採用一方法，非晶矽被 暫時地形成在一石英基體上，且膜被完全熱氧化以形成一 絕緣膜。此外，亦可使用一石英基體或一陶瓷基體，各具 有作爲絕緣膜之矽氮化物膜。 非晶矽膜9 0 2藉由低壓CVD方法、電漿CVD方 法或濺射方法而形成在基體9 0 1上。做成調整使得非晶 矽膜9 0 2的最終厚度（考慮熱氧化後的膜減小之後所決 定的膜厚度）成爲10至lOOnm(最好是30至60 nm)。在膜形成中，整體地管理膜中之雜質濃度是重要 的。 .在此實施例中，雖然在基體901上形成非晶矽膜. 9 0 2，亦可使用非晶矽膜以外的另—半導體薄膜。例如 ，亦可以使用矽與鍺的化合物S ixGei-* (〇<χ<1 本纸張尺度適用中囷國家標準（CNS>A4規格（210 χ 297公釐） -——I —II I Λ) - I I I I II I ^ !1 (請先閲讀背面之注意事項再填窝本頁> ------ 經濟部智慧財產局貝工消费合作社印製 45926 7 A7 -—__ B7 五、發明說明（20) )0 在此實施例的例子中，做成管理使得各c (碳）與N C氮）之濃度成爲小於5 X 1 〇18原子/cm3 (典型地 爲5 X 1 017原子/cm3或更小，最好是2x 1 〇17原 子/ c m 3或更小）’ c (碳）與N (氮）爲阻止非晶矽膜 9 0 2結晶之雜質’ 0 (氧.）之濃度成爲1 . 5 X 1 01β 原子/cm3 (典型地爲1 X 1 〇ls原子/cm3或更小， 最好是5 X 1 0 17原子/c m3或更小）。這是因爲如果 其中一個雜質的濃度超過上述値，雜質對於隨後的結晶會 有很壞的影響。在本說明書中，膜中之雜質元素的前述濃 度被界定爲S I MS (次離子質量分析）之測量結果。 欲得到上述構造，最好週期地執行使用於此實施例中 的低壓熱C V D爐之乾淸潔，使得淸潔膜成長室。藉著將 100至300 s c cm之C 1 F3 (氟化氯）氣體流入加 熱至約2 0 0〜4 0 0°C之爐，且藉著使用熱解所產生的 氟，而執行膜成長室之乾淸潔是恰當的。 據發明人所知，在爐中之溫度爲3 0 0 °C且C 1 F3 ( 氟化氯）氣體之流速爲3 0 0 s c cm之情形中，可在四 小時內完全移除厚度約2 之外皮（包含矽作爲其主要 成分）。 \ 非晶矽膜9 0 2中之氫的濃度亦爲一重要的參數，氫 含量越低，則得到越佳的結晶。於是，最好藉由低壓 CVD方法來形成非晶矽膜9 0 2。如果膜形成條件被最 佳化，亦可使用電漿C V D方法。 衣紙張尺度.適用中國國家標準（CNS>A4規格（210 X 297公釐） — — — — — — — — — ——-----11— ^- — — — — 1 — I —^)wl (請先間讀背面之注意事項再填寫本頁) A7 B7 d5926 7 五、發明說明（21 ) 閱 讀 背 面 之 注 意 事 項 再 填 % 本 頁 加入雜質元素（族1 3中的元素典型地爲硼，或族 1 5中的元素典型地爲磷）以控制在非晶矽膜9 0 2之膜 形成的TFT之臨界電壓（Vth)是有效的。需要決定在 .沒有加入用於控制Vth的上述雜質之情形中有鑑於V 11(所 加入的.量。 .接著，結晶非晶矽膜902。使用揭示於在1995 年五月1 9曰公告（申請於1 9 9 3年十月2 9日）之日 本專利未審査公告第He i 7 — 130652之技術作 爲結晶之手段。雖然可使用在此公告中之實施例1與實施 例2的兩種方式|最好使用公告之實施例2中所提出的技 術內容（揭示於在1 9 9 6年三月2 2日公告且申請於 1994年九月5日之日本專利未審査公告第He i 8 一78329)。在這裡參考包括說明書、申請專利範圔 、圖形與節要之日本專利未審査公告第He i 7 — 130652號與第He i 8-78329號所揭示的 整體內容。 經濟部智慧財產局具工消费合作社印製 依據日本專利未審査公告第He i 8 - 7 8 3 2 9 號所揭示之技術，首先形成一罩絕緣膜9 0 3，用於選定 製造非晶矽的結晶之元素的加入區域》罩絕緣膜9 0 3具 有許多開口，用於加入製造非晶矽膜之結晶的元素。藉著 " 開口的位置可決定結晶區域的位置。 包括鎳（N i )作爲製造非晶矽之結晶的元素之溶液 藉著旋轉塗覆方法被塗覆，以形成含鎳層9 0 4。可使用 鎳以外的鈷（Co)、鐵（Fe)、鈀（P d)、鍺（ - 本紙張尺度逋用中國國家標準（CNS)A4規格（210 X 297公釐） -5 6926 7 a? B7 五、發明說明（22 )· I! II Order · II ---- Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, A7, B7, 4-5926 7 V. Description of the Invention (12) t Read the notes on the back and fill in% This page 3 5 6 2 No. 3 and 8 reveal that the digital video data driving circuit is integratedly formed on the same substrate as the pixel matrix circuit and other driving circuits. The above patent discloses details of the operation of the digital video data driving circuit, which can be referred to to understand the operation of the digital video data driving circuit of this embodiment. The entire disclosure of Japanese Patent No. Hei 9-1 3 5 6 2 3 8 including the specification, the scope of patent application, the graphics, and the summary is here for reference. In FIG. 2, reference numeral 2 0 1 represents a synchronous counter, and A clock signal (ck) and a reset pulse (reset) are input. In this embodiment, the digital video data of 80 MW z supplied from the outside is divided into 8 segments, so digital video data of 100 MW z is generated. Thus, sixteen D flip-flops 202 are connected as shown in FIG. 2. The digital video data of 10 MHz generated by the digital video data driving circuit 110 is supplied to the latch circuit (1) 104, as described above. Printed by the Shellfish Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Referring again to Figure 1, the operation of the drive circuit on the brake signal line side will be described. Reference numeral 1 1 2 denotes a gate signal line side driving circuit A. The gate signal line side driving circuit A 1 1 2 includes a shift register circuit 1 1 3 and a buffer circuit 1 1 4. The shift register circuit 1 1 3 supplies a time signal to the buffer circuit 1 1 4. The buffer circuit 1 1 4 buffers the time signal from the shift register circuit 1 1 3 and supplies it to the gate signal line (scan line reference numeral 1 1 5 represents the gate signal line side driving circuit B, and has an AND gate. The signal line side driving circuit A 1 1 2 has the same structure. In this embodiment, the gate signal line side driving circuit is provided on both sides of the pixel matrix circuit 1.16 in this manner, and the two gate signals are operated. The line-side drive circuit makes this paper standard applicable to the Chinese national standard (CNS > A4 specification (210 X 297 public love) A7 B7 45926 7 V. Description of the invention (13) This embodiment can be operated even if one of them is not operated The pixel matrix circuit 1 16 has this structure, and the pixel TFTs are arranged in a matrix, and the number in the horizontal and vertical directions is 192 2 0 X 1 0 8 0. A screen (a frame) is used for scanning The number of lines is formed by repeating the foregoing. The operation is performed. In the active matrix type liquid crystal display device of this embodiment, an image update of 60 frames per second is performed. Here, a part of this embodiment (upper part) Copies) shift register circuit 1 0 2 and buffer A circuit diagram of the circuit 103 is shown in Fig. 3. Fig. 3 indicates a flip-flop (FF) circuit 102 "constituting the shift register circuit 102 and a part of the buffer circuit 10 constituting the buffer circuit 103. 3 ". In this embodiment, 240 flip-flop circuits 1021 constitute a shift register circuit 1 0 2. The flip-flop circuit 1 0 2" includes inverters 30 1 to 304 »Reference character ck Represents a clock signal. The reference character LR represents a scanning direction change signal. When the signal LR is high, a start pulse (S P) is supplied to the leftmost flip-flop circuit of the shift register circuit 102. 102 ", and the flip-flop circuit 102" transfers the signal from left to right. When the signal LR is low, a start pulse (SP) is supplied to the right-most flip-flop circuit (not shown), and the flip-flop circuit 1, 0 2 "Transfer the signal from right to left. The following will explain the situation when the signal LR is high as an example", that is, the flip-flop circuit of the shift register circuit 1 0 2 is operated from left to right. —Start pulse (S P) is input to the inverter 3 0 1. When the start pulse is input to the inverter 3 0 1, the inverter 3 0 1 is at time The paper size of this signal applies to China National Standard (CNS) A4 specification (210 X 297 public love) I ------------- Installation ------- Order ------- ( Please read the precautions on the back before filling in this page.) Printed by the staff of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the cooperative 45926 7 A7 B7___ V. Description of the invention (14) And the inverting clock signal (inverting ck) operate synchronously, and the inverting signal of the output input signal is inputted as the signal LR (high) in the inverter 3 0 2 * inverter 3 0 2 receives from the inverting The inverter 3 0 1 outputs the inverted signal. The inverter 3 0 4 receives the signal from the inverter 302 and outputs the inverted signal. Since the signal LR (High) is input to the inverter 3 0 3, it will not operate. In this way, the flip-flop circuit 102 "outputs a time signal to the NAND circuit 305. The time signal from the shift register circuit 102 (the flip-flop circuit 102") passes through the NAND circuit 305 and is input to Part of the snubber circuit 103 ". In this embodiment, a part of the buffer circuit 103 "includes five inverters 306 to 310. Although a part of the buffer circuit 103 "in this embodiment includes five inverters, the number of inverters in the present invention is not limited thereto, but may include a number of inverters smaller than five or greater than five . Printed by the Shelley Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs These five inverters 3 06 to 3 10 are each composed of TFTs with different sizes (channel widths). In this embodiment, the inverters 306, 307, and 308 are composed of TFTs each having a channel width of 30. Inverters composed of TFTs each with a channel width of 100 # m 3 9 9 and 3 1 0 * For the size of the TFTs constituting these inverters, the optimal size can be used through simulation * In addition, the display can be based on semiconductors The number of pixels of the device determines the optimal size of the TFT. Here, the inverter 3 07 will be used as an example for explanation. FIG. 4 is a circuit diagram of the inverter 307. The inverter 3 0 7 is composed of six P-channels. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 male *) · If ·! 45926 7 A7 B7 V. Description of the invention (15) TFT and six N-channel TFT. The channel width of each TFT is 30. Incidentally, it is appropriate that the channel width of these TFTs is made to be I 0 0 // m or less (preferably 90 or less). As shown in FIG. 4, the inverter 307 has a structure in which two inverter circuits are connected in parallel. Each inverter circuit is composed of two circuits, one of which includes three P-channel TFTs. They are connected in series (three-gate TFTs are used in the circuit), and three N-channel TFTs in another circuit are connected in series with each other (three-gate TFTs are used in the circuit). Similarly, when combining TFTs of many lines each having a small channel width (30 #m in this embodiment), compared with the case of an inverter composed of TFTs each having a large channel width , Can eliminate the undulation in TF T. In addition, heat generation and deterioration due to a large channel width can be avoided. Next, refer to FIG. 5. FIG. 5 is a circuit diagram * indicating a buffer circuit 1 1 4 of a gate signal line side driving circuit A 1 1 2 and a part (upper part) of a shift register circuit 1 1 3 in this embodiment, and pointing out The flip-flop circuits 1 1 and 3 ′ constituting the shift register circuit 1 1 3 and a part of the buffer circuit 114 ′ constituting the buffer circuit 114. In this embodiment, the shift register circuit 1 1 3 is composed of 1080 flip-flop circuits 11. 3 ". The inverter circuit 11 3 "includes inverters and phase inverters 50 1 to 504. The reference character ck represents a clock signal. The reference character LR represents a scanning direction change signal, and when the signal LR is high, a start pulse (SP) is supplied to the leftmost positive of the shift register circuit II 3 Inverter circuit 11 3 ". When the signal LR is low, a start pulse (SP) is supplied to the right-most flip-flop circuit. The paper size applies the Chinese National Standard (CNS) A4 specification < 210 * 297. Love > (Read the notes on the back of the poem before filling in this page) N Pack -------- Order --------. AUI. Printed by Shelley Consumer Cooperative, Intellectual Property Bureau, Ministry of Economic Affairs 459267 A7 B7 V. Description of the invention (16) (not shown) β (Read the precautions on the back before filling in this page) The operation of the shift register circuit 113 is the shift of the drive circuit on the source signal line side. The register circuit 102 is the same, so its description is omitted. The time signal of the self-shift register circuit 1. 1 3 (the flip-flop circuit 1 1 3 ′) passes through the NAND circuit 5 05 and is supplied to a part of the buffer circuit 114. The buffer circuit 114 "of this section includes three inverters 506 to 508. In this embodiment, although a part of the retarder circuit 114 · includes three inverters, the number of inverters in the present invention is not limited to this, and may include inverters whose number is less than three or greater than three. . The three inverters 5 6 to 5 8 are each composed of a channel width of 90, and a T FT of degree f. For the size of the TFTs constituting these inverters, the optimal size can be selected through simulation. The maximum size of the TF T can be determined according to the number of pixels of the semiconductor display device, etc. FIG. 6 is a circuit diagram of the inverter 508. The inverter 508 is composed of eight P-channel TFTs and eight N-channel TFTs. The channel width of each TFT is 90. It is appropriate that the channel width of these TF Ts is made 100 or less (preferably 90 or less). Printed by the Shelley Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, as shown in Fig. 6, the two circuits are connected in parallel with each other. ). In addition, "two circuits are connected in parallel with each other", and each circuit is constituted by two N channels T F T connected in series with each other (actually, a double TFT is used). Inverter 508 is composed of these circuits and is similar to this. When combining TFs with many lines each having a small channel width, it is the same as -iy-this paper size applies the Chinese national standard (CNS > A4 specification ( 210 X 297 ^) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Industrial Cooperatives d 5926 7 · a? __ __ B7____ V. Description of the invention (17) Inverter composed of TFTs each having a large channel width In contrast, the undulation in the TFT can be eliminated, and the current capacity can be ensured. In addition, heat generation and deterioration due to a large channel width can be avoided. FIG. 7 is a circuit diagram of the inverter 307 shown in FIG. 4. In FIG. 7, reference numerals 7 0 and 7 0 2 represent semiconductor active layers added with N-type impurities. Reference numbers 7 0 3 and 7 0 4 represent semiconductor active layers added with P-type impurities. Reference numeral 7 0 5 represents one Gate electrode wire, and A 1 (aluminum) including 2 weight percent of Sc (铳) is used in this embodiment. Reference numerals 7 0 to 7 1 1 represent a second wire and aluminum is used in this embodiment. Reference The number 7 1 2 represents a wire existing in the same layer as the gate electrode wire The dotted line typically represented by 7 1 3 is the part where the gate electrode is connected to the second wire, or the part where the semiconductor active layer is connected to the second wire * The reference numeral 706 represents GND and 707 represents VddH ( Power), 712 for OUT and 714 for IN. In the figure, it is assumed that wires with the same pattern exist in the same wire layer. The part indicated by the dotted line in the figure indicates that The shape of the hidden lower wire. In the inverter 307 shown in FIG. 7, although three P-channel TFTs and three N-channel TFTs are formed on the same semiconductor layer, a structure can also be adopted, and three independent The P-channel TF T and three independent N-channel TFTs are formed on separate semiconductor layers and are connected to each other by metal wires or via contacts. However, the area of the inverter 307 can be translated to this paper. Use Chinese National Standard (CNS) A4 specifications < 210 297 mm) --- ------- order ---- 1 (锖 Read the precautions on the back before filling this page) d5926 7 V. Invention description (18) is smaller, and the structure of this embodiment is The "Next, see Fig. FIG. 8 is a circuit pattern of the inverter 5 0 8 shown in FIG. 6. In Fig. 8, in addition to the inverter 508, a total of four inverters are indicated. In FIG. 8, reference numerals 801 to 808 represent semiconductor active layers added with P-type impurities. Reference numerals 809 to 8 1 6 represent semiconductor active layers added with N-type impurities. Reference numerals 81 7 to 8 2 4 represent gate electrode wires, and in this embodiment, A 1 (aluminum) including 2 weight percent of S c (重量) is used. Reference numerals 8 2 to 8 2 8 represent electric wires existing in the same layer as the gate electrode electric wires. Reference numerals 8 2 to 8 3 5 represent second electric wires, and aluminum is used in this embodiment. The dotted line portion typically represented by 8 3 6 is a portion where the gate electrode is connected to the second wire, or a portion where the semiconductor active layer is connected to the second wire. Reference numeral 829 represents VddH (high-voltage power supply), 832 represents GND, and 833 represents VddL (low-voltage power supply). Incidentally, each reference character I N1 to I N4 represents input, and each OUT1 to OUT4 represents output. In the figure, wires with the same pattern are made of the same material and exist in the same wire layer. The part indicated by the dotted line in the figure indicates the shape of the lower wire hidden by the upper wire. Here, the manufacturing method of the active matrix type liquid crystal display device including the driving circuit of this embodiment will be described. The described manufacturing method is a manufacturing method for realizing the present invention, and the active matrix liquid crystal display device of the present invention can also be realized by other manufacturing methods. This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) ί"ΐί Read the precautions on the back before filling in the lettuce page} "" Packing ------- Order ----- ^ lw_. Printed by the Ministry of Economic Affairs, Bureau of Labor and Economics, printed by the cooperative 45926 7 A7 45926 7 A7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economics, printed B7 5. Description of Invention (19) Here, see Figures 9 to 12 For example, many TFTs are formed on a substrate having an insulating surface, and a pixel matrix circuit, a driving circuit, a logic circuit, etc. are formed monolithically. In this embodiment, a state will be indicated in which a pixel that simultaneously forms a pixel matrix circuit accepts the CMO S circuit as a basic circuit of other circuits (driving circuits, logic circuits, etc.). In this embodiment, although the manufacturing steps for the case where each of the P-channel TFT and the N-channel TFT include a gate will be described, it is also possible to manufacture a TFT having a plurality of gate electrodes such as a double-gate or triple-gate TFT TFT CMOS circuit. Reference will now be made to Figures 9 A to 9D. First, a quartz substrate was prepared as a substrate having an insulating surface. Instead of using a quartz substrate, a silicon substrate on which a thermal oxide film is formed may be used. In addition, a method may be adopted in which amorphous silicon is temporarily formed on a quartz substrate, and the film is completely thermally oxidized to form an insulating film. Alternatively, a quartz substrate or a ceramic substrate may be used, each having a silicon nitride film as an insulating film. An amorphous silicon film 902 is formed on the substrate 901 by a low-pressure CVD method, a plasma CVD method, or a sputtering method. It is adjusted so that the final thickness of the amorphous silicon film 902 (the film thickness determined after considering the reduction of the film after thermal oxidation) becomes 10 to 100 nm (preferably 30 to 60 nm). In film formation, it is important to manage the impurity concentration in the film as a whole. In this embodiment, although an amorphous silicon film is formed on the substrate 901, another semiconductor film other than the amorphous silicon film may be used. For example, a compound of silicon and germanium can also be used. SixGei- * (〇 < χ < 1 This paper size is applicable to the Chinese National Standard (CNS > A4 specification (210 χ 297mm)--I -II I Λ )-IIII II I ^! 1 (Please read the notes on the back before filling in this page > ------ Printed by Shelley Consumer Cooperative, Intellectual Property Bureau, Ministry of Economy 45926 7 A7 ---__ B7 V. Invention Explanation (20)) 0 In the example of this embodiment, it is managed so that the concentration of each c (carbon) and NC nitrogen) becomes less than 5 X 1 〇18 atoms / cm3 (typically 5 X 1 017 atoms / cm3 Or less, preferably 2 x 1 〇17 atoms / cm 3 or less) The concentration of "c (carbon) and N (nitrogen) that prevent the amorphous silicon film 9 0 2 from crystallizing is" 0 (oxygen) at a concentration of 1.5 X 1 01β atoms / cm3 (typically 1 X 1 ols atoms / cm3 or less, preferably 5 X 1 0 17 atoms / cm3 or less). This is because if the concentration of one of the impurities exceeds the above-mentioned hafnium, the impurities may have a bad influence on the subsequent crystallization. In the present specification, the foregoing concentration of the impurity element in the film is defined as a measurement result of S I MS (Secondary Ion Mass Analysis). In order to obtain the above-mentioned structure, it is preferable to perform the dry cleaning of the low-pressure thermal C V D furnace used in this embodiment periodically, so as to clean the film growth chamber. A membrane growth chamber is performed by flowing 100 to 300 sc cm of C 1 F3 (chlorine fluoride) gas into a furnace heated to about 2000 to 400 ° C, and by using fluorine generated by pyrolysis. Dryness is appropriate. According to the inventor"s knowledge, in the case where the temperature in the furnace is 300 ° C and the flow rate of C 1 F3 (chlorine fluoride) gas is 3 0 sc cm, the thickness can be completely removed in about four hours. Sheath (contains silicon as its main ingredient). \ The concentration of hydrogen in the amorphous silicon film 9 02 is also an important parameter. The lower the hydrogen content, the better the crystal is obtained. Therefore, it is preferable to form the amorphous silicon film 902 by a low-pressure CVD method. If the film formation conditions are optimized, the plasma C V D method can also be used. Clothing paper size. Applicable to Chinese national standard (CNS > A4 specification (210 X 297 mm) — — — — — — — — — — — — 11 — ^-— — — — 1 — I — ^) wl (please read the notes on the back before filling this page) A7 B7 d5926 7 V. Description of the invention (21) Read the notes on the back and fill in% Add impurity elements on this page (elements in group 1 3 are typically boron , Or an element in the group 15 is typically phosphorus) to control the threshold voltage (Vth) of a TFT formed on the amorphous silicon film 902 is effective. It is necessary to decide that in the case where the above-mentioned impurities for controlling Vth are not added in view of V 11 (the amount added.) Then, the crystalline amorphous silicon film 902 is used. The use was disclosed in the May 19, 1995 announcement ( The technology of Japanese Patent Unexamined Publication No. Hei 7-130652, filed on October 29, 1993, is used as a means of crystallization. Although two types of embodiment 1 and embodiment 2 in this publication can be used Mode | It is best to use the technical content proposed in the second embodiment of the announcement (disclosed in the Japanese Patent Unexamined Publication No. He i 8 published on March 22, 1996 and filed on September 5, 1994 No. 78329). Reference is made here to the entire contents disclosed in the Japanese Patent Unexamined Publication Nos. He i 7 — 130652 and He i 8-78329 including the specification, patent application, drawings, and summary. Intellectual Property of the Ministry of Economic Affairs According to the technology disclosed in Japanese Patent Unexamined Publication No. He i 8-7 8 3 2 9, the local industrial consumer cooperative firstly forms a cover insulating film 9 0 3 for selecting crystal elements for manufacturing amorphous silicon. The joining area of the cover insulation film 9 0 3 has many openings The element used to add crystals for making amorphous silicon film. The position of the crystalline region can be determined by the position of the opening. The solution including nickel (N i) as the element for making amorphous silicon crystals is spin-coated. It is coated to form a nickel-containing layer 904. Cobalt (Co), iron (Fe), palladium (Pd), germanium (other than nickel can be used)-This paper uses China National Standard (CNS) A4 (210 X 297 mm) -5 6926 7 a? B7 V. Description of the invention (22)

He i 7 - 1 30652之實施例1所提出的技術之情 形中，單石地形成一可稱爲側向成長區之區域。然而’由 於原子核的產生在表面上是不規則的’很難控制結晶晶粒 邊界。 衣紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公；t ) 1 閲 讀 背 項 再 填 寫 本 頁 經濟部智慧財產局霣工消费合作社印製 45926 7 A7 _ B7 五、發明說明（23> 在結束結晶之加熱處理之後，罩絕緣膜9 0 3被移除 ，且執行做成圖案，使得形成由側向成長區9 0 7與 908做成的島狀半導體層（活性層）909、9 10與 9 1 1 (圖 9 C )。 這裡，參考數字9 0 9代表構成CMO S電路的N通 道TFT之活性層，9 10代表構成CMOS電路的P通 道TFT之活性層，且9 1 1代表構成圖素矩陣電路的N 通道TFT (圖素TFT)之活性層》 在形成活性層909、9 10與9 1 1之後*在其上 形成由包括矽之絕緣膜做成的閘絕緣膜（圖9 C)。 接著，如圖9 D所示，對於用於製造非晶矽膜之結晶 的元素執行一加熱處理（吸氣處理），以移除或減少用於 製造非晶矽膜（鎳）的結晶之元素。在此實施例中，鹵素 包含於處理氣氛中，且使用對於金屬元素有吸氣作用的鹵 素。 欲充分地得到鹵素之吸氣作用，最好在超過7 0 0 °C 的溫度下執行上述加熱處理。如果溫度不高於7 0 0 °C， 則很難分解處理氣氛中的氫化合物，所以恐性無法得到吸 氣效果。 、於是，在此實施例中，在超過700 eC，最好是 、 800至1000 °C (典型地爲950 °C)下執行加熱處 理，且處理時間爲0 . 1至6小時，典型地爲0 · 5至1 小時。 在此實施例中，指出一例子，其中在包括0 . 5至 本紙張尺度，適用中國國家標準（CN